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Monday March 4, 2019
Start the day right and enjoy the continental breakfast while networking with other attendees.
Welcoming remarks from the General Chair, Ira Feldman
“Test Challenges Accepted: Billions of Transistors, 5G Mobile, and End-to-end Quality”
Welcome to 2019! This year’s test challenges include early 5G production testing for millimeter-wave parts, deployment of 1149.10 USB scan, and the continued and relentless development of advanced process nodes. Not to mention the industry drive for very low defective parts per million (DPPM). The complexity of mobile phones now include digital integrated circuits supporting billions of transistors and millimeter-wave technology in 5G phones.
New engineering issues in the test arena include:
- The cost, characterization, test, and quality challenges being faced by the test engineers will all have different avenues of attack for success, however, they also have many similarities. To successfully enable chips with high yield and low DPPM, requires new learning in the area of outlier detection, new test techniques, new test hardware, and the search for improved fault models to extend the life of existing design for testability (DFT) technologies.
- The IEEE 1149.10 high speed Test Access Port (TAP)/USB enabled scan changes the traditional concept of limited pin testing for DFT testing, eliminates slow scan speeds, and introduces the need to constrain power to limit thermal rise during structural testing.
- Millimeter-wave testing is not new. However, enabling mm-wave testing for the mobile phone market at the volume, cost, and quality levels required for success is a new challenge for the industry. Serious manufacturing concerns revolving around interference, stray sources of activation, and enabling the multiband and modes to support the mobile phone, parallelism in test, and a host of other challenges are rising to the surface as the industry gears up for 5G.
Many of the solutions will use advanced data analytics and statistics. However, these alone will not solve the test engineer’s problems but will be an important part of their toolkit. This keynote will explore these industry challenges as well as innovative solutions being found across the industry.
Break & Networking
Enjoy the break and networking time.
Recent trends in the explosive growth of wireless data traffic makes millimeter wave (mmWave) communication the most attractive solution to this challenge in the next generation of “5G” mobile communication systems. Millimeter wave is an undeveloped band of the radio spectrum that can be used in a broad range of products and services like high speed, point-to-point wireless local area networks (WLANs), and broadband access. Millimeter wave is attractive for a variety of services on mobile and wireless networks, as it allows for faster than existing data rates up to 10 Gbps. Testing these high data rate brings unique challenges. The first presentation addresses these challenges by utilizing a hybrid cantilever and pogo technology to enable the shortest impedance controlled path from the tester to the device under test (DUT). Then the high speed problem is attacked via modeling and simulation in the second presentation. The effect of small changes in device location and its impact on key electrical performance criteria is examined in detail. AIP (Antenna in Package) is the new trend in IC packaging to support mmWave with the next presentation reviewing how to implement and test AIPs over the air test. The last presentation will expand on the challenges of over the air test with issues such as power amplifier efficiency, receiver sensitivity due to thermal changes, and more.
Post-silicon validation takes place between initial silicon power on (PO) and product launch. The main goal of validation is to verify product functionality against the Engineering Design Specification. The session starts with an overview of the MIPI Alliance and the Debug Working Group. In the second presentation, an introduction to the MIPI SneakPeek Debug Protocol supporting low-bandwidth interfaces (TinySPP) will be given. The presentation will show the differences between the TinySPP and FullSPP. The goal for the participant is to learn about the TinySPP Debug protocol and understand how it can be used in either a hardware or software implementation. In the third presentation, timing issues on I3C interface and multiple strategies for coping with them in instrumentation and platform design will be addressed. Benefits of a new industry specification that is being developed by the members of the MIPI Alliance’s Debug work group around using the MIPI I3C (an improved I2C) interface for debug and test that can communicate between the different components in systems/platforms will close the session.
Lunch is served. Enjoy the break and networking time.
Next-generation applications have continued to push advanced packaging technologies to achieve the required product performance. Wafer-level packaging, panel-level packaging, bumping, redistribution layers, fan out, and through-silicon vias are among the latest packaging technology becoming common as these new end applications grow in volume. Packaging will continue to explode with innovation and complexity to deliver the small-form-factor devices with powerful, high-speed functionality that consumers expect in next generation mobile electronics, healthcare, and other devices. This session begins with the challenges of testing biochips and biochemical microfluidic chips. Test procedure demands injecting different kinds of fluids on the sensor area for detecting and reaction during wafer probing under various temperature. The second presentation addresses the challenges of testing devices in frame/panel. These challenges include high coefficient of thermal expansion (CTE), local flexibility, and non-uniform heat distribution due to spaces in between devices. Next the challenges of efficiently testing gas sensors in high volume are presented. This, and other applications, have forced the rethinking of traditional test ‘solutions’. Lastly, as number of device pads/pins have increased along with the desired multisite parallelism the greater the required contact force. The final presentation looks at these challenges and potential solutions.
This session focusses on validation issues and techniques used in solving these challenges. Use of an innovative and custom interposer for validating high-speed LPDDR4 memory interface for package-on-package devices that also reduces motherboard design complexity will be presented first. The second presentation will explore the potential of using non-linear passive devices for accurate current measurements. This is critical to creation of a system with efficient power regulation for maximum battery life. Environmental stress tests are necessary tests to assess early package moisture sensitivity levels. The third presenter will cover case studies on these environmental stress issues and fails. The final presentation, an innovative and scalable architecture developed for high performance mid-bus probing for PCIe 4.0, 5.0 and beyond will be covered.
Poster Sessions are a great way to network through interaction with the poster presenters and other curious bystanders. At the same time enjoy the break refeshments and networking.
System level test (SLT) approaches test from a holistic level by using the device to test itself while often emulating actual customer usage. This is a drastic departure from traditional functional test which is typically targeted at testing for specific manufacturing defects and sensitivies . SLT requires the device under test (DUT) be placed in a socket on an application board that often uses the actual firmware, drivers, and operating system to test the DUT. The end result is an attempt to achieve a higher level of fault coverage in by using actual product hardware and software configurations. As each DUT requires its own hardware and software, standardization is a challenge. The first presenter will discuss how to mitigate this challenge and achieve common platforms. A unique view of how SLT and Burn-in fit together and can co-exist or overlap is discussed second. Lastly the challeges of 100% SLT at production as unit volume starts ramping is presented.
Validation and/or debug of new products by conducting different stress/environmental tests and developing different debug techniques is the focus of this session. Case studies on the functional stress failures that are encountered by conducting different environmental tests that are done as part of fab processing or a new product’s assembly packaging qualification flow will be presented first. The second presentor will show the evolution of the debug solutions in mobile systems addressed by MIPI and the USB organization. Lastly, an introduction of the different debug standards used for closed-chassis debug and to see how they create a complete solution will be discussed.
TestConX EXPO & Reception
The TestConX EXPO is a very popular part of the TestConX program with many great exhibits for connecting electronic test professionals to solutions. There is always something new to see or someone new to meet. Not to mention excellent food, drinks, and time for attendees to network with exhibitors!
Program subject to change without notice.