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Monday March 5, 2018
Start the day right and enjoy the continental breakfast while networking with other attendees.
Welcoming remarks from the General Chair, Ira Feldman
What failure rate is good enough? How reliable do today’s and tomorrow’s semiconductor devices and sensors need to be? How critical are failure rates and how are they evolving with increased customer demands for security, safety, and reliability? What is the impact of consumer confidence on industries such as automotive, personal health, and even mobile devices?
This keynote address dives into these questions and highlights challenges in our industry’s historical infrastructure and test methodologies. It provides the context for what we should all be asking ourselves: Are we really providing enough test coverage and assurance of reliability for new applications with higher quality and reliability requirements than ever seen before? Is this coverage sufficient to enable these applications to safely become pervasive over the next decade?
Break & Networking
Enjoy the break and networking time.
Today’s mobile users want faster data speeds and more reliable service. The next generation of wireless networks — 5G — promises to deliver that, and much more. These higher bandwidth and frequency requirements are driving the need for higher performance test solutions. Several new and innovative technologies to address these challenges will be presented. The challenges and improved contact solutions for wafer level chip scale packaging (WLCSP) radio frequency (RF) applications lead the way. This will be followed by RF characterization of contactors for these rapidly emerging high frequency markets. Innovative methods to optimize socket characteristics for automotive applications that are pushing the frequency limits to 90 GHz will then be covered. Lastly, techniques and best practices are discussed for measuring and evaluating a range of sockets for a 28 Gbps system
Billions of integrated circuits (ICs) produced worldwide go through burn-in processes to ensure reliability of the finished device. Specialized printed circuit boards (PCBs) known as burn-in-boards (BiBs) are the “workhorse” of the burn-in process. Gil Conanan will discuss unique PCB designs to eliminate potential damage to PCB traces and edge contacts which results in extremely high BiB scrap rates. Building device specific BIBs for qualifying new process technology at a semiconductor foundry is very expensive due to the constant change of devices and large number of processes qualifications. By designing a common or universal BiB for at least two or three sequential technology nodes, Krishna Mohan Chavali describes how this high qualification cost can be significantly reduced. Jun Lee Brosoto discusses an innovative BiB design that permits sharing of digital signal lines that was previously an issue for particular devices. Lastly, a unique approach to ultra-high power burn-in will be described by Joe Lin.
Lunch is served. Enjoy the break and networking time.
The interconnect industry faces significant challenges to continually develop innovative contact technologies to meet the ever increasing demands of the test market. Today’s technology challenges include flexibility to adapt to different package specifications, high current carrying capability, electrical transparency (extremely short height), and shielding for high- speed / high-frequency applications. Many innovative technologies with practical approaches will be discussed. Technologies covered include micro-electromechanical systems (MEMS) spring probe technology for wafer level chip-scale packaging (WLCSP) and flip chip applications, coaxial shielded contact design, low-height hybrid elastomeric contacts, and high current test contactors.
High-speed input/output (I/O) channels approaching 100 Gb/s are becoming common in today’s devices. Pad pitch is continuing to shrink. And thermal management of devices is becoming essential. Accurate device performance testing is impossible without proper design of printed circuit board (PCB) to accommodate all of these challenges. Don Thompson starts with a novel approach to addresses the miniaturization required in PCBs by fine pitch applications through 3D-printing of space transformers. A solution to the top side interfacing challenges of devices under test (DUTs) via a universal elastomer and probing PCB is shared by Stephanie Seaman. Bruce Mahler discusses the efficiency of embedding passive components inside the PCB to enable microfluidic and other applications for the control and test of ICs. Lastly, advanced techniques such as optimized pad stacks, connector launching pads, and via stub lengths to reduce resonance effects to address high-speed challenges are covered by Xiao-Ming Gao.
Poster Sessions are a great way to network through interaction with the poster presenters and other curious bystanders. At the same time enjoy the break refeshments and networking.
Advances in the semiconductor industry have led to smaller and higher frequency devices. To address these emerging complexities, new testing methodologies need to be developed to screen devices under test (DUTs) for defects that appear in real-world applications with minimal impact in terms of time and cost. System Level Test (SLT) is often implemented to ensure high quality end products with a target of zero-defect shipments. In this session, authors will discuss a variety of SLT methodologies and challenges that include accurately measuring system power at different workloads, testing of System in Packages (SiP) devices, and technological trends that are driving higher need for massively parallel System Level Test.
Accessing the signal pins can be difficult with ball grid array (BGA) and other packages due to the dense array and pitch miniaturization. Often a test interposer is integrated into a BGA socket to provide sufficient space for data acquisition on the main printed circuit board (PCB). Taekyun Kim will describe how a 3D MEMS probe construction was simulated and verified experimentally for use as a test interposer. Test interposers do present signal integrity challenges for high speed designs with issues such as unwanted reflections due to the their physical structure. An approach to resolve these issues with an on-board equalization methodology using embedded passives is explained by Xiao-Ming Gao. Lastly, Noel Del Rio will discuss next generation 28 Gbps SERDES application modeling challenges, material selection, and validation using a vector network analyzer (VNA).
BiTS EXPO & Reception
The BiTS EXPO is a very popular part of the BiTS program with many great exhibits to explore what is Now & Next in the test and burn-in of packaged semiconductors. There is always something new to see or someone new to meet. Not to mention excellent food, drinks, and time for attendees to network with exhibitors!
Program subject to change without notice.