TestConX 2021 Virtual Event

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May 3-7, 2021 Free Virtual Event


Welcome to TestConX 2021!

We are excited to bring the knowledge and expertise of TestConX directly to you via live interactive virtual presentations. And registration is free courtesy of our sponsors.

Be sure to reserve May 3-7, 2021 from 7 - 10 am Pacific time for each day's session. 

We are looking forward to having you join us in May!

Ila Pal & James Tong, Technical Program Co-chairs
Ira Feldman, General Chair
on behalf of the entire TestConX organization

 

Monday May 3, 2021
7-10 am PST/UTC-8

Session 1
5G/mmWave

5G/mmWave devices present significant challenges across semiconductor test industry, from instrumentation, material, test interconnects to HVM handling equipment. This session will start with an overview of 5G/mmWave testing, followed by a discussion on test platform and calibration techniques. We will take a deep dive on a socket and handler integration for OTA testing, then a comprehensive check on PCB design optimization for up to 70 GHz, and finish the session with a close examination of a novel structure of switching PCBs and contactors for mmWave testing.

“From 5G mmWave to 6G THz: What's Next in RF Test Challenges”
Jeorge Hurtarte
Teradyne
“Open Platform Prodution Test for mmWave/5G Devices”
Jon Semancik
Marvin Test Solutions
Dale Johnson
Marvin Test Solutions
“Socket Design and Handler Integration for High-Volume Over the Air Testing of 5G Applications”
Natsuki Shiota
Advantest
Jose Moreira
Advantest
Aritomo Kikuchi
Advantest
Hiromitsu Takasu
Advantest
“Optimized PCBs in a 5G World”
Don Thompson
R&D Altanova
“Package Testing of mmWave 5G Applications”
Jason Mroczkowski
Cohu
Aaren Lonks
Cohu

Tuesday May 4, 2021
7-10 am PST/UTC-8

Session 2
Big Data for Semiconductors & Market Reports

Big data and machine learning is seemingly everywhere, with the technology becoming pervasive. In this session we look at new forms of data collection enabling big data and its use to solve problems in the semiconductor industry, specifically machine learning algorithms are being utilized to investigate the causal mechanisms of customer returns in a test flow of semiconductor manufacturing environment (resulting in Big Data). We also take time to come up to speed the other ‘big’ dataset as we do every year, the marketplace report and outlook!

“Marketplace Report”
Ira Feldman
Feldman Engineering
“Market Outlook”
John West
VSLI Research
“Big Data”
Rahima Mohammed
Intel
“Production Wafer Probe of 77-81 Ghz Automotive Radar Applications”
Jason Mroczkowski
Cohu
Marty Cavegn
Cohu
Jory Twitchell
NXP
Poster Session
Poster Session

“The Channel Branching Technology with Fan-Out Buffers for Implementing a High Parallelism Probe Card”
Yun-Hyok Choi
SungKyunKwan University
Jun-Pyo Lee
SungKyunKwan University
Gyu-Yeol Kim
Samsung Electronics Company
Byung-Sung Kim
Semiconductor Building
“Reusable ATE Interface - Making the Most out of Uni-Board(mDIB)”
Senthilkumar Dhamodharan
Caliber Interconnect Solutions Pvt Ltd
Mohanasundaram "Mohan" Selvaraj
Caliber Interconnect Solutions Pt Ltd
“Optimal Localization of DC/AC Relay Chips in a High Parallelism Probe Card for ENhancement of SIgnal Integrity”
Junhee Han
SungKyunKwan University
Kwangho Kim
SungKyunKwan University
Gyu-Yeol Kim
Samsung Electronics Company
Wansoo Nah
Sungkyunkwan University
“Achieving 54+ Ghz Using Optimized Socket Architecture with Traditional probe technology for low cost-of-test”
Jason Mroczkowski
Cohu

Wednesday May 5, 2021
7-10 am PST/UTC-8

Session 3
Contact Technology
Contacts

Contact technology plays a critical role in making stable electro-mechanical contact from the semiconductor processor to the PCB, with critical challenges rising from denser pitch on the lands/solder-balls, higher pin and I/O count, larger package size, RoHS lead-free, shortening of time-to-market, cost control. In this session, we will start with proposing a structure to prevent crosstalk of elastomer sockets to improve transmission losses and reduce costs. Second presentation will be on understanding resistance fluctuations in contacts under high current loading. Third presentation will show how important lower ground inductances are to devices performance operating at high frequencies that affect device test yields. Final presentation will be on the importance of using high frame rate microscope cameras in a test environment for motion studies.

“Coaxial Elastomer Socket for Crosstalk”
Justin Yun
TSE
Dave "Dave " Oh
TSE
Seungho Woo
TSE
Yunchan "YC" Nam
TSE
“Resistance Flucuations in Contacts Under High Current Loading”
Gert Hohenwarter
GateWave Northern Inc.
“Package Grounding Effects on Electrical Test Performance in Contactors”
Jeff Sherry
Johnstech International
“High Frame Rate Cameras for Motion Study Testing”
Michelle Joyce
Johnstech International
“Bridging the Gap, Part 2”
Dong Weon "Dan" Hwang
HiCon Co., Ltd.
Noel Del Rio
NXP
Paul Schubring
HiCon Global

Thursday May 6, 2021
7-10 am PST/UTC-8

Session 4
Meeting High Performance Need
Validation

This session will discuss solutions including an alternative low cost approach that lets the user source analog signals using pre-existing high-speed digital instruments, challenges on testing Bluetooth earphone device in ATE, modeling and measurement of high bandwidth devices with minimized error, and a roadmap and expectations for 30-70 GHz signals in a load board or probe card. You will also learn about a new high performance PCB interposer design used for evaluating different PAM4 SERDES performance without the need to redesign the validation platform. Finally, a new socket design for desktop CPUs will be discussed for enabling higher CPU frequencies.

“'Dancing Over Digital-Analog Dichotomy' - Engendering Analog Signals from Digital Channels”
Senthilkumar Dhamodharan
Caliber Interconnect Solutions Pt Ltd
Mohanasundaram "Mohan" Selvaraj
Caliber Interconnect Solutions Pt Ltd
“Demonstrating V93000 WSMX_HR Analog Performance Requirement in TWS Application”
Hersy Liu
Advantest
“Design and Analysis of a High-Performance PCB Interposer for 100G PAM4 Validation”
Xiao-Ming Gao
Intel
“Modeling Measurement of High Bandwidth Device”
Nozar Naing
Texas Instruments
“A New Desktop Socketing Approach to Boost Operating Frequencies”
Emad Al-Momani
Intel

Friday May 7, 2021
7-10 am PST/UTC-8

Session 5
Take the big picture
System Level Test

Creating a reliable and performant test-cell is a challenging task, independent of if it is for system-level test, final test or wafer probe configuration. Many different aspects need to be considered to become successful. In this session, we will put the spotlight on four specific areas from all three test areas. We will start with a look at System-Level test, before taking on the challenge of large fan-out for wafer probe heads. Next we will understand why electro-static discharge management is critical to the test industry, and we will finish with an in-depth look into the technology of elastomer contactors.

“System Level Test Needs, Requirements, and Equipment”
Richard "Rich" Karr
Texas Instruments
“Design Strategy for Achieving a Transparent Probe-Head”
Sventlana Sejas
SV Probe
“ESD Compliant Contactors and Optimized Test Performance”
David Skodje
Johnstech International
Emerson Reyes
Analog Devices
Reul Cruz
Analog Devices
“Advanced Elastomers. for ATE/SLT Test”
Junho "JH" Lee
ISC
Hyeonyoung Kim
ISC
Mike Dell
ISC
Poster Session
Poster Session

“Unleashing the Magic of Parallelism in ATE”
Senthilkumar Dhamodharan
Caliber Interconnect Solutions Pvt Ltd
Mohanasundaram "Mohan" Selvaraj
Caliber Interconnect Solutions Pt Ltd
“AI Chip Structure Test Challenge and AI Application Test Coverage Enhancement on ATE”
Corning Zhu
Enflame-tech
Winston Zhang
Enflame-tech
Jason Cao
Enflame-tech
“Computational Simulation of Current Carrying Capacity of Contacts”
Ming Li
Johnstech International
“Evolution of High-Performance Spring Probes”
Lambert "Bert" Brost
Technoprobe
Free Registration

Program is subject to change without notice.