TestConX China 2019


Tuesday October 29, 2019

InterContinental Shanghai Pudong Hotel
No.777 Zhangyang Road
Pudong New Area Shanghai, SH, 200120
People's Republic of China



Please arrive early to check-in and pickup your conference badge and materials prior to the program start.


Tomson Ballroom
Opening Remarks

“Welcome to TestConX China 2019”


Tomson Ballroom

“The Future of Advanced Packaging: Meeting the Challenges”
Jan Vardaman
TechSearch International, Inc.
Abstract - Biography (English)

The high cost of moving to the next semiconductor technology node is changing the role of packaging and assembly in the electronics industry. New packaging solutions are being adopted to achieve the economic advantages that were previously met with silicon scaling. These options include silicon interposers, fan-out wafer level packages, and system-in-package. Some high-performance options are considered homogeneous integration, where die are partitioned. Others are classified as heterogeneous integration, including solutions in which some die functions are fabricated on the latest nodes, combined with other die fabricated on older less expensive nodes and linked together in the package. Combinations of memory and logic in the same package are increasingly common. Substrate warpage remains an issue and the need for known good die is becoming increasingly important. Test considerations factor into package choices. This presentation discusses the packaging changes and how the industry is addressing these challenges

E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided market research and technology trend analysis in semiconductor packaging since 1987. She is the co-author of How to Make IC Packages (by Nikkan Kogyo Shinbunsha), a columnist with Printed Circuit Design & Fab/Circuits Assembly, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She is a senior member of IEEE EPS and is an IEEE EPS Distinguished Lecturer. She is a member of SEMI, SMTA, IMAPS, and MEPTEC. She received the IMAPS GBC Partnership award in 2012 and the Daniel C. Hughes, Jr. Memorial Award in 2018. She is an IMAPS Fellow. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.

摘要 - 简介 (Chinese)

半导体技术进入下一个拐点的高成本正在改变封装在电子行业中的作用。正在或将要采用的新封装技术可获得经济效益,它正如以前半导体规模化生产一样。这些技术包括:硅晶作为中阶层,扇出式晶圆封装和System in package。一些高性能的技术被认为是均体合成,但晶片要被切割分离。其他是异体合成,例如,一些晶片的功能是分散到多个晶片相联的结点上。后者可应用传统的较便宜的技术,存储器和逻辑芯片的相结合日益广泛。芯片基座的挠曲仍是一个问题,采用已知好的晶片进行封装变得更加重要。测试的要求也是选用封装形式的考虑因素。本文将介绍封装形式的变化和行业如何解决这些挑战。

作者简介:E Jan Vardaman是TechSearch International, Inc的创建人和总裁。从1987年开始,公司为市场提供半导体行业研究和技术的趋势分析。她是《怎样制造半导体封装》一书的作者之一,是《线路设计和制造》杂志的专栏作者,并发表有很多出版物。她也是IEEE EPS的高级会员及特邀演讲嘉宾,是SEMI, IMAPS和MEPTEC的成员。曾于2012被授予IMAPS GBC合伙人奖,2018年获得Daniel C. Hughes Jr.纪念奖. 是IMAPS研究员。在建立TechSearch前,曾就职于Microelectronics和计算机技术公司(MCC)——电子行业第一家非常有竞争力的研究单位。

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Jan Vardaman
President and Founder
TechSearch International Inc.
E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided market research and technology trend analysis in semiconductor packaging since 1987. She is the co-author of How to Make IC Packages (by Nikkan Kogyo Shinbunsha), a columnist with Printed Circuit Design & Fab/Circuits Assembly, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She is a senior member of IEEE EPS and is an IEEE EPS Distinguished Lecturer. She is a member of SEMI, SMTA, IMAPS, and MEPTEC. She received the IMAPS GBC Partnership award in 2012 and the Daniel C. Hughes, Jr. Memorial Award in 2018. She is an IMAPS Fellow. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.


Session 1
Tomson Ballroom
Market Report

“Getting ready for the next wave of growth”
Hanning Shi
VLSI Research
Abstract - Biography (English)

Powerful growth drivers are emerging which will propel the semiconductor industry to even higher levels. This strong growth combined with new chip designs, new manufacturing technologies and new packaging solutions will result in great opportunities for those companies that are ready to catch the wave.
This presentation explains what is happening in the market and what steps your company needs to take to ensure they do not miss out on this critical moment. Specifically, it provides insights based on the application of in-depth data analysis techniques to quantify the actual prospects for suppliers of test and burn-in sockets. A particular focus will also be paid to the role of China and Chinese test consumable suppliers in the coming era of big data.

Hanning Shi is a Technical and Market Analyst at VLSI Research Europe. She joined VLSI Research Europe in 2015. She has a MPhil degree in Industrial Systems, Manufacturing and Management from the University of Cambridge and was awarded a first-class degree with honours in BEng Mechanical Engineering from Cardiff University.

摘要 - 简介 (Chinese)

本次报告将阐述当前的市场趋势以及贵公司需要采取的应对措施,以确保不会错过这个重要时机。 具体而言,报告将提供一些基于深度数据分析的见解,以量化测试座和老化插座供应商的实际前景。其中,中国及其本土供应商在即将到来的大数据时代所扮演的角色将会被重点关注

石瀚宁是VLSI Research Europe的技术与市场分析师。她在2015年加入VLSI Research Europe。在这之前,她获得了剑桥大学工业系统制造与管理的硕士学位和卡迪夫大学机械工程的一等荣誉学士学位。

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Enjoy time to meet with the presenters and network while refreshments are served.


Session 2
Tomson Ballroom
5G and mm-wave Test Challenges
High frequency challenges for next generation applications.
“Challenges of Over the Air (OTA) Testing with ATE”
Jose Moreira
Jan Hesselbarth
University of Stuttgart
Krzysztof "Kris" Dabrowiecki
Abstract - Biography (English)

In this presentation we will discuss the challenges of over the air testing (OTA) of DUTs with Antennas in Package (AIP). The topics that will be discussed are:

  • Near Field vs Far Field Measurements
  • OTA Challenges for ATE
  • The Surrogate Package Concept as verification vehicle for OTA
  • Types of Measurement Antennas
  • Limitations of Single Antenna Socket Approaches
  • Probing in the antenna reactive nearfield

The above topics will be discussed using measured data from a surrogate package designed with antennas in the package to serve as evaluation vehicle. Because this surrogate package designed by Advantest has no silicon, only the antennas is the package is an ideal demonstration vehicle. There is no IP restrictions on the measured data with that surrogate package making it an ideal vehicle for comparing different OTA testing approaches

Jose Moreira is a senior staff engineer in the HW R&D Team of the SOC business unit at Advantest in Böblingen, Germany. He focuses on the challenges of testing high-speed digital, silicon photonics and 5G mmwave devices, especially in the area of PCB test fixture design, signal and power integrity, measurement techniques and focus calibration. He joined Agilent Technologies in 2001 (later Verigy and in 2011 acquired by Advantest) and holds a Master of Science degree in Electrical and Computer Engineering from the Instituto Superior Técnico, Lisbon University, Portugal. He has multiple published papers and patents and he is a senior member of the IEEE. He is also co-author of the book “An Engineer’s Guide to Automated Testing of High-Speed Digital Interfaces”.

摘要 - 简介 (Chinese)

将讨论在带天线芯片的测试( over the air testing ,OTA)。主题包括:

  • 近域和远域测量
  • OTA自动测试中的挑战
  • OTA标调测试件的优用封装芯片
  • 测试天线的类型
  • 单个天线测试做的缺点
  • 不同的方法

将用代用封装芯片测量数据来讨论上述主题,Advantest 开发的此封装件没有硅胶芯片,但有天线是理想的标调测试件,测试数据无知识产权限制,从而可以比较不同的OTA测试方法。

Jose Moreira 是资深工程师, 在德国的Advantest 公司中SOC事业部的硬件开发组,重点在高速数据芯片,硅光子和5G毫米波芯片,尤其在PCB设计,信号和功率合成,测量技术和校正,2001年入职Agilent Tech, 后由Advantest 收购,拥有电子和计算机硕士,葡萄牙的里斯本大学,是IEEE的资深会员,发表多篇技术文章和专利,是“An Engineer’s Guide to Automated Testing of High-Speed Digital Cuter faces”的作者之一

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“Mass Production Solution: Coaxial Socket for 112 Gbps PAM4”
“同轴结构用于112Gbps PAM4测试”
Best Presentation
Collins Sun
WinWay Technology Co., Ltd.
Ryan Chen
WinWay Technology Co., Ltd.
Hayden Chen
WinWay Technology Co., Ltd.
Abstract - Biography (English)

The world is connected in the digital data era with novel mmWave applications, such as 5G and WiGig, which will drive the dramatic demand of high performance for 400 Gbps Ethernet instrument. The original modulation technique based on Non-Return-to-Zero (NRZ) encoding cannot provide enough effectiveness to process the increasing volume of data. Therefore, 4-Level Pulse-Amplitude Modulation (PAM4) application doubles the density of data in serial data transmissions by increasing the number of levels of pulse amplitude, which leads to a possible and cost-effective development for the networking infrastructure. However, the Signal-to-Noise Ratio (SNR) of PAM4 is worse than NRZ and needs a better cross-talk reduction with better mechanical characteristics for mass production.
In this presentation, we have worked with Tier-1 customers in the world to test 112Gbps PAM4 chips with pitches ranging from 0.5 to 0.8 mm. If we compare test results among the coaxial socket, short probe and elastomer solution, the short probe and elastomer solution are common test solutions to fulfill the high-speed requirement. However, both contact methodologies would not be adequate for mass production. Brownie socket* has unique design of the coaxial structure where insulated composite is embedded. Compared with other existing coaxial solutions, Brownie is capable to be manufactured for the fine pitch coaxial socket.
To analyze the socket performance, we have done the socket simulation alone based on the high-speed area of the device. The result of socket itself shows the insertion loss around -0.2dB, return loss around -16dB, and crosstalk <-50dB @28GHz. In order to have better understanding of channel signal loss, we have been working on the channel simulations of the socket and critical traces of the PCB for comparing with actual measurement results. Based on the test results, three kinds of sockets can pass at 56Gbps level and their performance is about the same. However, for 112Gbps PAM4, coaxial socket is better than short probe in the eye opening and has longer contact travel with better contact stability in the production environment. On the other hand, elastomer does not have clean eye opening for zero Bit Error Rate (BER) at 112Gbps PAM4.
In summary, coaxial socket is a proven mass production solution for 112Gbps PAM4. Both electrical and mechanical characteristics of coaxial sockets meet the testing requirements.

Collins Sun received his PhD of physics from National Sun Yat-Sen University and was senior R&D Manager at WinWay Technology, who is in charge of new product development and technology research.

摘要 - 简介 (Chinese)

世界变成了毫米波的数据时代,如5G和WI Gig,它推动了400 Gbps Ethernet 仪器的巨大需求,原有的Non-Return to Zero (NRZ)已不能满足要求,因此,PAM4变成了网络架构的主要数据传输方式,但是PAM4的信号噪音比不如NRZ,需要在机械装置中减小Cross talk 噪音)。
本文将介绍112Gbps PAM4 芯片 (0.5~0.8mm针脚) 的测试,比较了同轴结构,短针和导电弹性胶。短针和导电弹性胶可以满足高速的要求,但大量生产中不能满足机械接触的要求。Brownie 测试座是注入绝缘体的同轴结构比较其它现有的同轴结构,Brownie使小阵脚的同轴测试座成为可能。
采用了芯片高速进行测试座高频性能的模拟Insertion Loss,~ -0.2 dB, return Loss 16dB, cross talk < -50 dB @ 28GHZ.又进行了测试座通道和PCB的模拟,并与测量结果比较,根据实验结果,三种类型的测试座可以通过56Gbps, 但是, 112Gbps PAM4,同轴结构要优于短针并因更大的压缩长度而接触更可靠和稳定,另一方面,导电弹性胶在112Gbps PAM4的银圈上没有明显的张开区域。
总之,同轴测试座已证明是112Gbps PAM4 芯片大批测试中的解决方案,固同时解决了电和机械的芯片测试性能要求。

Collins Sun 是国立孙逸仙大学的物理博士,在WinWay 公司作高级研发经理, 从事新产品的开发。

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“Review today’s test strategy on ATE and SLT”
Liang "Neil" Zhang
Abstract - Biography (English)

Advance process and highly integrated SOC device require for more test coverage than before. This presentation will Review this change and propose new approach for high throughput SLT test and method for complex IP debugging on ATE.

Mr Zhang Liang graduated and got master degree from Fudan University. He worked in ATE industry for more than 10 years. His role in company has been application manager, training manager in different company and now take the position as technical marketing manager In Teradyne China.

摘要 - 简介 (Chinese)

先进工艺和高集成SOC芯片需求较之前更多的测试覆盖。本文将介绍这种测试的趋势变化,并且提出了新的 高产出SLT解决方案和新方法来应对复杂的IP调试。

张亮先生硕士毕业上海复旦大学。他从事ATE相关工作超过10年。他曾在不同公司担任过工程开发经理,培训经理等职位,目前就职于 泰瑞达公司,担任市场技术经理。

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Lunch and TestConX EXPO

Enjoy the delicious hot buffet lunch and networking time. Then take the time to explore the TestConX EXPO. There will be many great exhibits to connect electronic test professionals to solutions. You will be certain to see something new or meet someone new. As attendees to TestConX know, there is always excellent food, drinks, and time for attendees to network with exhibitors! TestConX EXPO will open at 12:15 and will remain open throughout the afternoon until 18:00


Session 3
Tomson Ballroom
Extreme Testing
Thermal control, pressure testing, and low current measurements for accelerated life testing.

“Cooling Solution for IC Device Testing”
Huagju Miao
Smiths Interconnect
Quynh Nguyen
Smiths Interconnect
Abstract - Biography (English)

Semiconductor industry has made great progress in past 20 years. Nowadays the chips are fabricated with billions of transistors and these transistors generate much more heat which cause high heat power dissipation. So chip cooling has become a big challenge for IC Test Industry. In this article, some typical cooling solutions will be introduced, such as metal heatsink cooling, fluid cooling & chiller, heat pipe cooling, etc.
Air Cooling
Heatsinks (HS) always touch IC and press onto socket/PCB to test. For lower power IC test, free air goes through HS tunnels to chill the system. For higher power IC test scenario, HS can’t meet our Temperature request, then it is needed to add an electronic FAN on HS to force cooling the IC Test system.
Water cooling
Heatsinks still can be used in water cooling. Additionally, HS have more tunnels design in its body for water flowing; the tunnels can be made as: series, parallel, pseudo-series, pseudo-parallel. Heat dissipation for HS with water tunnel can overwhelm the air cooling one.
Another method is to add a chiller system to improve the heat dissipation ability for the thermal management proposal.
Heat pipe cooling
HS can be a part of heat pipe cooling system. HS body has several heat pipes inserted upwards. It is the evaporation and condensing of the water that forms a pumping action to move the water (and thus the heat) along the pipe.
Challenge Heat pipe cooling
HS can be a part of heat pipe cooling system. HS body has several heat pipes inserted upwards. It is the evaporation and condensing of the water that forms a pumping action to move the water (and thus the heat) along the pipe
The future IC test power will be as high as 1000W or more, then new lid cooling system is a direction of research; Socket cooling ability is still not proficient

Huaqiu “Terence” Miao* is a Mechanical Engineer at Smiths Interconnect Suzhou from 2014. He has over 15-years experiences about mechanical design. Currently his role is designing IC test products and thermal analysis.

摘要 - 简介 (Chinese)

散热片也可以是热通道冷却系统的一部分。 散热片本体被多个热通道向上接入。正是水的蒸发和冷凝形成了泵送作用,使水(以及热量)沿着管道流动。
* 将来的芯片功率可能高达1000W或者以上,所以新的散热方式任然在探索当中……
* 测试插座的散热方式正在捉襟见肘。
* 空间,
* 成本

缪华秋(Terence), 2014年加入史密斯英特康苏州事业部,是一名机械工程师。他有超过15年的机械设计经验。当前他主要从事芯片测试产品的设计和热分析

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“MEMS Pressure Sensor Testing Solutions and Challenges”
Cheng-Wen "Hank" Yao
Kuang-Hsiang Liu
Li Kang Cheng
Abstract - Biography (English)

MEMS Pressure Sensor Testing Solutions and Challenges
Thanks to MEMS (micro-electromechanical systems) technological advances, the applications of automotive electronics, consumer, IOT, mobile device have become more flourishing. MEMS pressure sensors already gained a foothold in market and played an important role in navigation, Quadcopter, environmental monitoring and TPMS… applications. Due to the huge demand for pressure sensors, develop testing and calibration solution to keep abreast of deal with new developments in the MEMS sensor.
This presentation will introduce our achievements of testing calibration systems for MEMS pressure sensor. How to control temperature and pressure will be crucial factors in the MEMS pressure testing, we have to face more challenges of soaking time reduction, chamber temperature uniformity, high pressure chamber design, leakage issues and stable time. The temperature close-loop control and cooling system are used for the purposes of optimal soaking time. In this system, precise temperature control and efficient cooling system become more important. In addition, chamber can fine-tune temperature offset for each area by modular temperature control unit, that temperature uniformity within +/-1⁰C had been achieved. For pressure chamber stability, reliability and leakage, we improved the chamber design to give greater strength and rigidity. Chamber volume is a trade-off between pressure stability and response time for different pressure conditions; Chamber volume problem are simulated, which proves optimization of pressure control time and accuracy.
As previously mentioned, this system has multi chambers for different temperature conditions and also control the heat loss that will make good performance to pressure sensor. For efficient mass production, multi chambers simplify the process of high/low temperature testing, and that reduce the opportunity for operator error.

Cheng-Wen "Hank" Yao currently is Department Deputy Manager of Advance Technology Development Division of King Yuan Electronics Co., Ltd. He has worked for KYEC over six years since he received his Master of Science (M.S.) Electronic Engineering degree from National Ilan University and is responsible for MEMS testing technology development. His experience includes integration of software and hardware systems for MEMS testing solutions for mass production of accelerometers, gyroscopes and pressure sensors, and magnetic sensors.

摘要 - 简介 (Chinese)

因微機電製程的進步使得微機電傳感器 (MEMS Sensor)的之應用發展日趨蓬勃,舉凡汽車電子、消費電子、移動裝置、互聯網等都脫離不了其應用範疇。而利用微機電系統技術所製造之壓力傳感器,更已在市場中佔有一席之地,諸如車用導航、四軸飛行器、環境監控、胎壓計等應用都有著密不可分關係,也因此對於製程的進步讓在MEMS測試技術與校正環境的建置開發上則顯得極為重要。
在多腔體機構設計上,首先,溫度控制部份是透過溫度回授感測與散熱系統來縮短升降溫的時間,而精準溫控變化與散熱效率將為關鍵;設計中對腔體的均溫性採用控溫模組來進行各區域微調以達+/- 1℃內;再則,壓力測試部分則強化腔體機構設計增強壓控穩定度與可靠度,減少漏氣產生,透過模擬腔體容積優化實驗,取捨於壓力穩定與反應速度上,讓壓力精準度與測試時間成本達到最佳化。

姚承汶目前服务于, 京元电子尖端测试技术开发处 . 承汶在京元电子工作已超过6年, 自從研究所畢業獲得硕士学位. 他目前擔任MEMS产品测试技术整合部门副经理 ,主要負責MEMS产品的CP/FT测试程式开发及 MEMS测试解決專案的系统軟硬體整合。在测试 MEMS加速度计、陀螺儀、壓力计与磁力计..等, 有很豐富的量产经验. 硕士 / 电子工程学系 / 国立宜蘭大学 .

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“HAST In-Situ Electrical Tests Down-to Pico-Ampere Range”
Yi-Ming Lau
STAr Technologies
Choon-Leong "CL" Lou
STAr Technologies
Abstract - Biography (English)

The traditional method of Highly Accelerated Stress Test (HAST) or Temperature Humidity Bias (THB) is to stress the devices at high voltage, high temperature and high humidity chamber. Devices are then powered down and cooled back to room temperature at intermediary predetermined stress time to be tested at ambient conditions by an external electrical test system. Once the electrical characterization is completed, the devices are put back to the chamber and powered back again to the stress voltage at HAST or THB conditions for the next cycle of stressing.
This qualification process ensures the devices tested are not affected by degraded DUT boards, sockets, interconnects and cable assemblies inside the HAST chamber. This process is not only time consuming, but more importantly, are extremely laborious and lack missing real-time electrical test results on the functionality and performance of the devices during stress.
There are more devices requiring low-level leakage current measurements and high voltage stress. To date, there are no known DUT boards, sockets, interconnects and cable assemblies that can work in HAST or THB chambers that are capable of high isolation. This is especially so for electrical measurement requiring pico-Ampere leakage current under high temperature and humidity conditions. As such, no electrical measurements or characterizations can be done in-situ during the HAST and THB. This further means that there is no immediate accessibility of precision electrical data throughout the stress cycle.
In this presentation, we put up a qualified set of DUT Boards, sockets and cable assemblies that are fully capable to work under high temperature and high humidity conditions, and yet still able to provide low leakage electrical measurements with leakage down to 10pA/V level. Each of these parts are independently qualified and put together as a burn-in interface under HAST and THB without much degradation and thus will not impact the actual in-situ test of DUTs during stress.
In this presentation, we will also show the results in-situ electrical measurements throughout HAST and THB, even down to pico-ampere level measurements. The DUT interfaces are designed and developed with proven data to be able to provide low leakage electrical characterization, and continuous electrical monitoring capability under high temperature and humidity.
With this system and setup, users would not only be able to have the electrical data to understand the changes of the devices throughout the qualification process, but also save the time and uncertainties induced on the devices after powered down and transferring of the devices to another system for electrical measurement after each stress cycle.

Yi-Ming Lau is the Senior Director of the R&D Department of STAr Technologies. She joined STAr in 2005, and has since served as the Product Manager for STAr Reliability Test Systems. She is responsible for the development and integration of advanced reliability test solutions, as well as applications and sales support for reliability systems. She holds a Masters of Engineering & Bachelor of Engineering in Electrical Engineering from National University of Singapore, and a Diploma in Law with a Mark of Credit from University of London (External). Prior to joining STAr, she worked as a Senior Failure Analysis Engineer with Micron Semiconductor Asia, responsible for device level failure analysis.

摘要 - 简介 (Chinese)


劉毅敏是一位資深處長, 服務於思達科技股份有限公司之研究開發部門. 她於2005年加入思達科技, 從思達的半導體可靠度測試系統的產品經理開始做起. 她負責高階半導體可靠度測試系統解決方案的開發與整合, 也同時負責系統可靠度測試的應用及業務端的支援. 她擁有新加坡國立大學電子工程之碩士學位, 以及倫敦大學法學专科學歷. 在進入思達以前, 她任職於美光半導體資深故障分析工程師, 負責半導體器件故障分析.

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Networking Break

Enjoy additional time to meet with the presenters, network, and explore the TestConX EXPO further. There will be many great exhibits to connect electronic test professionals to solutions.


Session 4
Tomson Ballroom
Planning Ahead
Doing the up-front work for reliability, debug, and simulation.
“Embedding Reliability for Zero Field Failures”
Nigel Gordon Kissaun
ELES Semiconductor Equipment
Abstract - Biography (English)

Several technology market trends are driving semiconductors to more stringent reliability requirements. The continued pervasion of electronics in automotive due to electrification, connectivity and autonomous driving is increasing dramatically the number of ICs in each car. This is coupled with an increase in chip complexity and pressure to shorter time-to-market cycles. Also, as is well known, Integrated Circuits reliability follow the bathtub curve. In its central region, the bathtub curve has the lowest, approximately constant, failure rate. Failures occurring in this region are defined “random” and are not detected by the traditional test flow (Final Test + Qualification & EFR test). As shown in literature, the majority of these, called “intermittent failures”, may be activated and deactivated by voltage, frequency, and operating temperature variations, in other words by stress conditions. The existing IC qualification flow and testing flow during manufacturing are no longer adequate to meet the higher functional safety or mission critical requirements. Even a 1ppm failure rate is too high. Not detecting random and intermittent failures, for such applications the traditional reliability flow and traditional test flow are therefore not suitable, obliging to adopt mitigation strategies such as redundancy. This paper describes a holostic reliability test approach called RETE (Reliability Embedded Test Engineering), which encompasses aspects from both AEC-Q100 and AEC-Q004. It starts with DfRT (Design for Reliability Test) at Design stage, a strategy for TFR (Test for Reliability) implementation, and data analysis to support a Learn-from-Fail feedback cycle. Practical applications of RETE to different semiconductor segments are described, supporting the road to zero defects.

Nigel graduated from London's UCL in Electronics Engineering & Computer Science in 1985, followed by postgraduate research in Semiconductor Reliability. He worked for STMicroelectronics in Malta in Test Engineering functions including Technical Director, and as Corporate Testing Director for worldwide manufacturing based in Singapore. He occupied the position of President & General Manager of ON Semiconductor for their two manufacturing plants in Philippines, and is currently responsible for Strategic Business Development at ELES Semiconductor Equipment, Italy.

摘要 - 简介 (Chinese)

本文要介绍“Holostic”可靠性测试,称之为RETE(Reliability Embedded Test Engineering).它综合AEC-Q100和AEC-Q004,它从设计阶段开始采用DFRT(Design for Reliability Test)和TFR战略(Test for Reliability)及数据分析来支撑Learn-from-Failure循环。此方法在半导体产品的实例将在演讲中介绍。

Nigel G Kissaun 1985年毕业于伦敦的UCL 电子工程和计算机系并从事半导体可靠性研究(postgraduate). 在STMicro (Malta) 从事多项测试工程相关职务,包括技术总监,全球芯片制造测试总监(新加坡). 他曾担任On Semi在菲律宾二????制造工厂的总裁和总经理. 目前担任在意大利的ELES Semi Equipment 的商业发展总监。

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“Cloud Based Remote Debug”
Seong Guan "SG" Ooi
Intel Corporation
Siew Cuong Chang
See Tien "Angie" Ng
Abstract - Biography (English)

Limited quantity of first article silicon and customer reference board (CRB) to support silicon debug or test is a challenge in semiconductor industry today. Semiconductor manufacturer did not produce huge quantity of first article silicon due to technology instability and involved huge manufacturing cost. The situation become more challenging when the manufacturer extended the debug/test coverage to their customer, example shipping limited silicon to their customer who resides in different geographical location which may caused up to weeks of delay and impact the overall time-to-market (TTM).
Current Technology Limitation:
Some 3rd party remote access software like TeamViewer & VNC were used by the manufacturer to establish a virtual debug environment with their customer to address the silicon/CRB limitation issue. Typically, these connections are done thru a non-secure internet connection and may lead to Intellectual Property (IP) leak.
Intel has come out with a breakthrough solution by introducing a cloud based remote debug (CBRD) infrastructure which allow external customer to have first-hand access to first article silicon debug. The entire CBRD concept is to establish an end to end debug experience to all the user, which covers connectivity, CRB configuration/setup/booking system, remote debug experience and automated testing capabilities. This solution consists of 2 major architectures: Secure Access & Board Farm. CBRD applied 4 layers of Multi Factor Authentication (MFA) for secure access. Each user will need to register in Intel database to obtain an online certificate & login credential to establish a secure VPN tunnel to Intel’s environment. Board Farm architecture consists of asset management system, platform scheduling system with auto OS provisioning and extensive remote debug features such as remote power cycling for a platform, remote DC & RF signal probing & BIOS post screen access & debug. Individual debug environment can be create by the administrator on the fly. CBRD operates in 24x7 and allow user to perform debug activities remotely, anytime and anywhere. With this solution in placed, early bugs or sightings can discovered and Intel can response to the fix in a much more early stage to reduce the number of silicon design stage – a new agile way for silicon debug process.
Conclusion & Implementation:
This solution is able to improve the silicon debug process by weeks, reduced the total numbers of CRB and first article silicon produced per project (>50% hardware cost savings), improve the lab operation to 24x7 (improve utilization) and accelerate the time to market for a new product release. Intel has received a huge demand from customer to extend this capability across the globe.

SG Ooi holds a bachelor’s Degree in Electronics Engineering. SG starts his career with Teradyne Inc. as Field Application Engineer before joined Intel. SG hold several technical positions throughout his career in Intel and his current position is the staff technologist and product owner for global post-silicon. SG expertise are in mix signal device debugging and end to end system design. SG is a certified SAFe Agilist and also an active technical paper author with more than 20 technical papers published for internal and external technical conferences. SG also hold a patent in Smart Sensor solution for IoT.

See Tien "Angie" Ng graduated with Master in Engineering (major in microelectronics) from Multimedia University Malaysia. She currently pursue a part time doctorate study with University Science Malaysia. Angie is Technical Lead for Intel Malaysia Internet of Things Group, a certified FUSA Automotive Engineer and also comes with 22 years industrial working experience.

摘要 - 简介 (Chinese)

主题词: 模块和芯片测试挑战—测试自动化
少量的首批芯片样品和测试用户参考线路板是半导体测试行业中进行芯片测试调试时的一个挑战,芯片制造厂由于工艺的不稳定和制造成本而不顾意提供很大数量的首样,由于担心测试调试成本的增加和影响产品上市时间, 这个挑战变的更大。 芯片制造厂可以利用第三方的远程切入软件,如TeamViewer 和VNC 进行模拟调试环境和其客户共同解决首样数量不足和参考线路板的问题。由于数据传输通过非安全的外部网络,从而担心知识产权的保护问题。
解决方案:英特尔采用了云基远程调试(cloud based remote debug, CBRD)的突破性技术。客户可以直接切入进行首件芯片调试。这个系统的基本概念是所有的调试经验可以提供给使用者,它包括了连接性,参考线路板架构/设定和远程调试经验和自动测试的能力,此解决方案由二个主要架构组成: 安全切入和板植入(Secure Access & Board Farm)。CBRD 有四层多因子验证确保安全性。每一个用户需要在英特尔的数据库上注册取得授权去建立一个安全的VPN通道进入英特尔数据库,板植入架构则由下列分支组成:资产管理,平台计划系统可自动OS分部或广泛的远程调试和功率循环,远程DC 和RF信号测定和BIOS 适屏调试。个别用户调试环境由管理户远程建立。CBRD是7天24小时运行,用户可任何地点任何时候进行远程调试,此系统的使用, 有助于芯片的研发早期的调试和问题的解决,从而减少了芯片调试的时间和成本。
CBRD系统的实际应用使芯片研发调试时间缩短数周,芯片首样和参考线路板数量减少 (50% 以上成本降低) ,改善了实验室操作成为24x7 (充分使用) ,加速了新产品开发和上市的时间,英特尔已经全球众多产品要求去拓展此系统的能力。

SG 拥有电子工程学位。加入Intel前在Teradyne Inc 任客户服务工程师。在Intel 担任过不同的技术职务,目前担任全球“post-silicon”资深技术专家和产品负责人。SG专长是复合信号芯片的故障分析排除和终端间的系统设计。SG 是注册SAFe Aglist并在内部和外部的技术会议上发表20余篇技术文章。拥有一个用于IoT的智能感应会的专利。

Angie毕业于馬来西亚的Multimedia University, 微电子专业硕士。目前在University Science Malaysia 攻读博士学位。Angie 是Intel Malaysia IoT 部门的技术领导,拥有FUSA注册工程师, 和22年企业工作经验。

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“Improve Socket Performance by Simulating Embedded Device S-parameter”
Yuanjun "YJ" Shi
Abstract - Biography (English)

IC test engineer like to using inductance and capacitance for socket model to debug and run analysis for their circuitry. This is simple way to evaluate the socket performance base on the extracted value of lump RLC. And most of the time the inductance plays more important role compare with capacitance.
In this paper, we report a basic study on various ways to extract the inductance of a socket model, and discuss the difference across varies math models.
Next by study a Saw filter application case, we discuss how correlation of these models compare to embedded s-parameter. We proposed several designs base on the embedded s-parameter math model to improve the socket. The experimental results confirmed the simulation data and proven embedded s-parameter is more correlated the real test result, and provide better prediction of socket design change.

Yoinjun Shi is currently CTO of Twinsolution Technology Shanghai Inc., He has Bachelor Degree of electronic engineering from Suzhou University and MBA from Victoria University Switzerland. Yoinjun has over 15 years’ experience in the semiconductor industry. Now Yoinjun’s major focus is on developing high quality metal contactors. He is a member of the BiTS China Technical Program Committee.

摘要 - 简介 (Chinese)


Yoinjun Shi 施 元军目前是上 海韬盛电子科技股份有限公司的研发经理。他在半导体测试产业有超过15年 的经验,并致力于测试连接器对信号和电源完整性影响研究多年, 他还多次提交并获得专利。其中以高 隔离度的测试插座的研发最具代表性。现在他主要专注于开发低接触电阻和长寿命的金属接触探针。

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