Call for Presentations

Call for Presentations and Posters for
TestConX 2025
March 2-5, 2025 - Mesa, Arizona

Join us for the 26th annual TestConX workshop to be held in-person on March 2-5, 2025. There will be daily technical presentation sessions and a TestConX EXPO where you will find the latest in test products and solutions. Don’t miss the preeminent event focused on connecting electronic test professionals to solutions.

The TestConX Technical Program Committee is seeking presentations that highlight the challenges and solutions for a broad range of test and burn-in topics. Test applications of highest interest include:

  • Machine Learning / Artificial Intelligence
  • Internet of Things
  • Power & Automotive Semiconductors
  • Battery Test
  • Photonics
  • Smartphone & 5G/6G including antenna in package (AiP) and mm-wave 

Each PRESENTATION at TestConX is provided a thirty-minute presentation slot (approximately 25 minutes for the presentation with 5 minutes for questions and answers). And authors only need to prepare a PowerPoint presentation. (There is no paper to write.)

POSTERS provide an opportunity to directly interact with the attendees during the reserved session(s). Each poster is three oversized 24" W x 36" H pages that illustrates the technical challenge and solutions.

Please submit a 250-to-500-word abstract for presentations or posters of your original, previously unpublished, technical presentation by September 31, 2024.

Submit abstracts by October 1, 2023 to recieve a thank you gift and be entered into our Early Bird prize drawing.*


Submit via:


Abstracts will be reviewed and authors will be notified around October 18, 2024.

Presentation submissions are due January 5, 2024.

Topics that address the challenges of these and other test applications include, but are not limited to:

Electrical, Mechanical, & Thermal Challenges in package testing

  • High frequency and high data rate techniques and technologies including 5G and mm-wave
  • Wafer Level Packages (WLP) and Panel Level Processing (PLP)
  • High current, high voltage, high power, high power/current density, and/or high temperature device testing
  • Handler & change kit designs and considerations
  • Fine Pitch Kelvin Contacting
  • Thermal management and modelling
  • Contact technology
  • Bare Die, system on a chip (SOC), system-in-package (SiP), and 2/2.5/3D package testing
  • Wafer level chip scale (WLCSP) test for Known Good Die (KGD) or final test

Test Process & Operational Challenges 

  • Over the Air (OtA) and Antenna in Package (AiP) testing
  • System Level Test (SLT)
  • Test & Burn-in floor operations
  • Socket repair, cleaning, and re-plating methods
  • Massively parallel and non-singulated test (Wafer Level and Panel Level)
  • Test strategies for reducing qualification and production time
  • Socket & PCB verification, checkout, & qualification
  • Strip Testing and Test-in-Tray
  • High reliability testing for mission critical and medical applications
  • Microelectromechanical system (MEMS) and non-electrical (optical, fluidic, magnetic, acoustic, etc.) stimuli testing
  • Bring-up, characterization, and validation
  • Cloud and big-data analytics
  • Design for testability including ATE test, SLT, and reliability test
  • Failure analysis

Module & Product Test Challenges

  • Fixturing and test contact
  • Test automation
  • Automated material handling
  • Wireless testing at scale / high volume
  • Thermal control
  • Battery test and characterization
  • Quantum computing

Printed Circuit Board (PCB) Design & Manufacturing Challenges 

  • Advanced via structures (coax, optimized, micro via, etc.)
  • For high temperature Burn-in board applications
  • High data rate test applications
  • Space Transformers and Ultra-fine pitch
  • Board to Board Interconnects
*Abstracts need to be accepted and presented at the event in order to recieve thank you gift and enter Early Bird prize drawing. Void where prohibited by law or company policy.