Virtual Event November 21 - 23, 2023
TestConX has, over the course of its twenty-four-year history, established itself as the preeminent event for test consumables, test cell integration, and test operations. The program scope has expanded over these years from packaged semiconductor “final” test and burn-in to encompass all practical aspects of electronics testing including validation, advanced packaging testing, system level test, module test, and beyond to finished product test.
Last year, the 8th annual TestConX China 2022 was held as a virtual live on-line event with excellent presentations and question and answer sessions.
Don’t miss this opportunity to be part of TestConX as we connect a larger community of test professionals and to participate in this excellent event!
See additional Sponsorship Opportunities below.
TuesdayNovember 21, 2023 - 0900 to 1130 Shanghai/CST
The project involves using AI Techniques including NLP to extract the key information/solution from the IPS ticketing cases and convert into FAQs for quick reference. Most IPS tickets contain lengthy and some unconstructive conversation between the engineer and the customer. Previously, engineers had to review the whole conversation and find out the solution. After that, they need to manually create the Q&A for future reference. With this solution, Q&A for each ticket will be created automatically as per scheduled time after the ticket was closed for the customer to enquire. Therefore, this will save time and manual effort of the engineers. This project provides full automation process starting from fetching the ticket information from the IPS website until converting the ticket information into Q&A. With the use of API, we can feed the Q&A into any solutions that can display the Q&A search results e.g., QIRI and Avaamo chatbot.
This presentation covers a lot of ground and provides a quick update of the important changes happening in the world of burn-in and test sockets.
Topics explored on the market side include acquisitions, market drivers, and the regional shifts that are reshaping the industry. From the technology perspective, the presentation explains how advanced packaging, demanding thermal test conditions, and the introduction of data analytics are adding cost and complexity to semiconductor test.
The project involves using AI Techniques including NLP to extract the key information/solution from the IPS ticketing cases and convert into FAQs for quick reference.
Most IPS tickets contain lengthy and some unconstructive conversation between the engineer and the customer. Previously, engineers had to review the whole conversation and find out the solution from the conversation. After that, they have to manually create the Q&A for future reference. With this solution, Q&A for each ticket will be created automatically as per scheduled time after the ticket was closed for the customer to enquire. Therefore, this will save time and manual effort of the engineers.
This project provides full automation process starting from fetching the ticket information from the IPS website until converting the ticket information into Q&A. With the use of API, we can feed the Q&A into any solutions that can display the Q&A search results eg. QIRI and Avaamo chatbot.
The presentation introduces Schematic AI Extractor and how it assists the reviewer in reviewing and mining the data from schematic file.
A schematic file usually contains lots of interfaces such as audio, display, memory, and so on. For each interface, there are details such as vendor, part number, voltage, technology type, and so on to be extracted. The Schematic AI Extractor can reduce some of the manual labor from the reviewer.
The Schematic AI Extractor provides automatic extraction along with AI to interpret the extracted data of the components. Next, the details will filter using a similarity checking character by character with a threshold value method and a master list that contains details of the components. Once everything is passed, will be exported to a custom Excel sheet used by the reviewer.
WednesdayNovember 22, 2023 - 0900 to 1130 Shanghai/CST
The automotive and AI HPC market are going through a revolution. With the growth, challenges come for ATE supplier to meet the high voltage, high current and precision measurement requirements for these semiconductors. ADVANTEST 93K already developed and released different kinds of VI cards, such as, DPS128, AVI64, FVI16 and XPS128/256 to meet test requirements above.
These instruments are both kelvin structure inside which guarantee the accuracy when test. Therefore, it’s necessary to consider highly accurate kelvin when we design load board according to instruments’ specification. This paper will also introduce different kelvin test methods and comparison between.
Meanwhile contact resistance should be absolutely considered during wafer test. Fritting can be an option when contact resistance between probes and wafer can’t be ignored.
Besides, some special or innovative solutions will be designed in the load board and testing application. These innovative solutions have been successfully applied in the customer production projects and gotten a good performance. the paper will explain it from the test theory, test solution design, test program and test results.
Plastronics is now part of Smiths Interconnect. Plastronics had sought to use the T033 H-Pin in plastic as a replacement for elastomeric interconnects due to its 1mm test height. With the Smiths team, access to data on elastomers is available for review. The thought was to perform testing to a T033 interposer and compare the data and see how well the T033 interposer performs in FDR cycle data through long term cycling.
Data is available on two different elastomers we will call elastomer A and elastomer B. We will perform similar testing to The T033 H-Pins so we can do a comparison of FDR data. We are assuming all three sets of data will perform equally well initially, but the elastomeric should show major resistance increases as cycles continue due to elastomeric compression set. The T033 H-Pin interposer should also show increase in resistance as well, but only very slight as compared to the conductive elastomers. If this proves to be true, we will move on to comparing RF data and seeing if the T033 performance in this area is equally as good as the elastomers. RF data would be created by modeling first, then followed up by actual test results. We will get a comparison of how well the models work to real world data. We will also get a comparison of the T033 RF performance to the Elastomers. This paper will initially target the mechanical part of the testing, but we will follow up with the electrical data for a future presentation if all goes as expected.
ThursdayNovember 23, 2023 - 0900 to 1130 Shanghai/CST
As one important ATE supplier, we will also face some testing challenges like the high parallelism，low cost control, test time and different types automotive devices from the semiconductor manufacturer based on the fixed configuration, which also inevitably bring with higher requests for test solution. As you know, test cost and test time are the key elements for semiconductor manufacturers. Therefore, for better performance we need to consider some special or innovative solutions on the load board in advance, that can help reduce cost and test time by matching with code optimization.
This paper will introduce the solutions from some real cases which have been successfully applied to the customers production projects and gotten a good performance. There will be showed the test principle, hardware connection, test code and test time comparison in the following provided solution.
Current RF applications, especially for mmWave case, faced challenging the signal performance, PCB design, manufacturing capability and simulation accuracy.
For general non-mmWave RF design, usually routing signal trace on PCB surface layer for below advantage: a. avoids add via in signal path to get better performance; b. lower design Dk and lower propagation delay; c. wider line width and lower loss.
But to mmWave design, application case needs route mmWave signal trace in PCB inner layer with via for below requirement: a. fanout many (example: more than 10ea) concentrated RF signals, even signal pins surrounded by ground pins, make signals can’t fanout on surface layer; b. small device pitch(<=0.35mm) need substrate board to convert device pitch to 1mm or more. So, mmWave design need use substrate board/ PTH via in signal path, it will put forward higher requirements for hardware design.
This presentation introduces some hardware experience on 26~47GHz mmWave signal delivery structure with plated through hole (PTH), it will focus on PTH via and board stack-up structure, trace length balance, fabrication considering and simulation optimization. This presentation uses an substrate and PCB design as an example and introduce some general PCB design methods with PTH for mmWave design.
In high-speed digital PCB, differential pairs are widely used to suppress power noise. The working characteristics of differential mode and common mode can be described and observed in the form of mixed mode S parameters. Among them, for SDD parameter, optimizing the impedance matching can help reduce signal reflection and improve transmission quality. For SCC, SCD, and SDC parameters, theoretically, modal transformation can be suppressed by reducing the asymmetry of the transmission path. The asymmetry of the path may come from the environment of vias, wiring method, placement of serial components in path, inter-pair skew, length match position and tune length.
To explore how to optimize SCD and SDC parameters, a pair of 32Gbps differential loopback signals with RC components in series was selected and a series of simulation experiments are conducted. By changing the above variables, the influence of inter-pair skew and symmetry of differential pairs on transmission quality was studied, and the following conclusions and optimization ideas were obtained:
- 1. The different distribution of ground and power in the environment of PN vias can cause impedance asymmetry. The longer the asymmetric via length, the larger the PN skew. Optimizing the position of GND vias and reducing the length of the asymmetric vias can optimize SCD and SDC parameters.
- 2. The relative position of PN components in the path will affect wiring. Keeping the relative positions of PN vias at different areas in the pathway consistent can reduce the asymmetry of wiring.
- 3. As for wiring, loose coupling routing has wider linewidth and smaller attenuation in long-distance applications. However, in the case of small pitches, using tightly coupling routing can achieve more symmetrical fanout.
- 4. Instantly PN length matching can reduce the influence of inter-pair skew, but in tight coupling routing, it will also cause impedance mismatch of differential pairs. Appropriate position and tune length of length match can reduce impedance mismatch and reduce the impact on SDD parameter.