TestConX Korea 2023


Incheon, South Korea - November 7, 2023

Central Park Hotel Songdo
193, Techno Park-ro, Yeonsu-gu
Incheon, Korea, 406-840
Tel. +82-32-310-5010~1


TestConX has, over the course of its twenty four-year history, established itself as the preeminent event for test consumables, test cell integration, and test operations. The program scope has expanded over these years from packaged semiconductor “final” test and burn-in to encompass all practical aspects of electronics testing including validation, advanced packaging testing, system level test, module test, and beyond to finished product test. 

This year is our inaugural annual TestConX Korea event!

Don’t miss this opportunity to be part of TestConX as we connect a larger community of test professionals and to participate in this excellent event!




“Opening Remarks”
Ira Feldman
Feldman Engineering
Session 1
Market Reports

“AI Revolutionizing Semiconductor Testing”
Panchami Phadke
Abstract (English)

The rapid advancement of Artificial Intelligence (AI) has emerged as a pivotal driving force in the semiconductor industry, fundamentally transforming the landscape of semiconductor testing. This study delves into the symbiotic relationship between AI and semiconductor testing, with a comprehensive analysis of various segments of semiconductors. Moreover, this research extends its purview to the global probe card market, accentuating region-specific insights for two key players: Korea and China.

In semiconductor testing, AI has evolved from an auxiliary tool to a central catalyst, significantly enhancing testing efficiency, accuracy, and speed. The memory segment, encompassing DRAM and flash memory, has reaped the rewards of AI-driven testing with remarkable defect detection and error prediction. Similarly, non-memory components like logic and analog devices have witnessed the infusion of AI algorithms for adaptive testing and anomaly detection, reducing production bottlenecks.

Another essential aspect of this project is the introduction of a new probe card taxonomy and re-segmentation of the Probe card market. This innovative classification promises to redefine industry standards, fostering a more coherent understanding of probe card functionalities and applications. While the global probe card market thrives, specific focus is directed towards Korea and China. These semiconductor powerhouses exhibit unique market dynamics, propelled by local demand, innovation, and strategic collaborations.

In summation, this study underscores the indispensable role of AI in propelling semiconductor testing towards unprecedented heights and global Probe card market update.

“Market Dynamics and Technology Trends Affecting Burn-in and Test Sockets”
John West
Lin Fu
Abstract (English)

This presentation covers a lot of ground and provides a quick update of the important changes happening in the world of burn-in and test sockets.

Topics explored on the market side include acquisitions, market drivers, and the regional shifts that are reshaping the industry. From the technology perspective, the presentation explains how advanced packaging, demanding thermal test conditions, and the introduction of data analytics are adding cost and complexity to semiconductor test.


Break & Networking

Enjoy time to meet with the presenters and network while refreshments are served.

Distinguished Speaker

“Necessity to change the structure of the tester to cope with the increase in test cost & space in the future.”
“중장기 Test Cost & Space 증가 대응을 위한 Tester의 구조 변경 필요성”
Keumhyun Yu
Samsung Electronics
KH Yu headshot

유금현 Principal Engineer, Test개발그룹장

유금현 Principal Engineer, Test개발그룹장
2002 삼성전자 주식회사
2013~2016 삼성전자 중국 소주법인 Test 엔지니어
2020~2022 Test혁신 Project Leader
2023~ Test 개발 그룹장

20+ years
2002 Samsung Electronics Co., Ltd
2013~2016 Dispatch engineering service to China
2020~2022 Test Innovation Project Leader
2023~ Head of Test Development Group

Session 2
AI Revolutionizing Semiconductor Testing

“Standardization of Electrical Specifcations for Test Socket Contactors”
“Test Socket용 Contactor의 전기적 사양 표준화: 필요성과 표준화 방안 제시”
Elec Seo
Abstract - Biography (English)

In this presentation, we discuss various types of contactors used in semiconductor and electronic component test sockets. These contactors come in different shapes and are manufactured through various processes, including the widely used Spring pogo pins, Elastomer, Rigid types, among others. Test engineers in semiconductor and electronic component manufacturing companies select contactor types based on the characteristics of the Device Under Test (DUT), with particular attention to their electrical properties.

The presentation provides examples and explanations of electrical specifications for different contactors. Additionally, we explore the issue of contactor suppliers presenting varying electrical specifications, even when using the same contactor and housing. Through this analysis, we aim to assist test engineers in making more objective decisions when choosing contactors.

Furthermore, we offer examples of how to determine contactor electrical specifications using Spring pogo pins, including empirical measurements and Finite Element Method (FEM) Simulation Tools. This underscores the importance of standardization in measurement and simulation methods, helping test engineers in semiconductor and electronic component manufacturing companies make more precise contactor selections.

Ultimately, this presentation seeks to provide valuable insights and guidance for both test engineers and contactor manufacturers, streamlining the process of determining electrical specifications for contactors.

  • TONGMYONG UNIVERSITY, Mechatronics Master(2007)
  • PUKYONG NATIONAL UNIVERSITY, Electrical PH.D, Candidate(2009)
  • HITACHI DECO, Tester & Handler R&D Engineer(3Y)
  • LEENO Inc, Electrical Engineer (12Y)
  • Qualmax Testech Inc, Test socket R&D Engineer (10Y)
  • Current, ISC Co.,Ltd & Prowell, Test socket R&D Engineer (4Y)

추상적인 - 전기 (Korean)

본 Presentation에서는 반도체 및 전자부품용 Test socket에 사용되는 다양한 Contactor의 종류에 대해서 다루고 있습니다. 가장 많이 사용되고 있는 Spring pogo pin을 비롯하여 Elastomer, Rigid type 등의 형상과 제조공정에 따른 다양한 종류의 contactor가 사용되고 있으며, 반도체 및 전자부품의 제조업체의 Test엔지니어들은 DUT의 특성에 따라서 Contactor의 Type를 선정하고 있습니다. 특히, 전기적 특성에 따라서는 더욱 신중한 선택이 이루어집니다.

본 Presentation에서는 다양한 Contactor의 electrical specification과 관련하여 예시를 제시하고,각 Specification을 설명합니다. 또한, 동일한 Contactor와 Housing을 사용하더라도 Contactor 공급사들이 다른 Electrical specification을 제시하는 문제에 대해 고찰합니다. 이러한 고찰을 통해 Test 엔지니어가 보다 객관적인 판단으로 Contactor를 선택할 수 있도록 도움을 주고자 합니다.

더불어, Spring pogo pin의 실측과 FEM Simulation Tool을 활용하여 Contactor의 Electrical specification을 결정하는 방법의 예시를 설명합니다. 이를 통해 측정 표준 또는 시뮬레이션 방법의 표준화의 필요성을 이해하고, 반도체 및 전자부품 제조업체의 Test 엔지니어가 보다 정확하게 Contactor를 선택할 수 있도록 돕고자 합니다. 또한 Contactor 제조업체들도 Electrical specification을 결정할 때 고민을 덜어주는 프레젠테이션을 목표로 하고 있습니다.

  • 동명대학교 메카트로닉스공학 석사(2007),
  • 부경대학교 전기공학 박사과정 수료(2009)
  • HITACHI DECO, Tester & handler 개발 엔지니어(3년)
  • LEENO INC, 전자 엔지니어(12년)
  • Qualmax, 개발 엔지니어(10년)
  • 현재, ISC & Prowell, Test socket 연구개발 엔지니어(4년)

“Metal Insulator Transition Materials for Advanced Socket Applications”
“고성능 소켓용 금속절연천이소재”
Hansang Kwon
Next Generation Materials Co., Ltc
Abstract (English)

The semiconductor test socket is one of the mandatory final processes for achieving a high-quality chip. There are two types of test sockets widely used: pogo pin and silicon rubber sockets. Silicon rubber socket and pogo pin types depend on the desired application target. Pogo pin type is a traditional semiconductor test method that is over 40 years used in this field. This method can flow stable electric current and a relatively good lifecycle. The silicon rubber type is developed with a micro-ball located into the silicon rubber, showing relatively good results in the short high-frequency application field.

Most test socket materials use polymeric and ceramic-based materials. The socket materials have not been very critical even though semiconductor technology is developed faster than the test socket field till now. Thanks to nanotechnology could achieve a highly integrated narrow nanosized circuit design, but it also consumed high power with high thermal concentration. Those issues could cause some side effects of the chips, such as malfunctioning when used. Due to the above reasons, the test socket field could require better-performed socket materials such as a high-power adaptive with good thermal durability.

In this study, we have successfully fabricated the metal insulator transition materials with high thermal and power adaptive semiconductor test socket materials by powder metallurgy process.

추상적인 - 전기 (Korean)

반도체 테스트 소켓은 고품질 칩을 얻기 위한 최종 공정에 사용되는 필수 소재부품이다. 일반적으로 널리 사용되고 있는 테스트용 소켓 방식은 포고 핀과 실리콘 고무를 활용하는 형태이며 적용 대상에 따라 각각의 방식의 소켓을 선택적으로 사용할 수 있다. 포고핀 방식은 반도체 테스트 소켓 분야에서 약 40년 이상 사용되어 온 전통적인 테스트 방식이다. 이 방법은 안정적인 전류를 흘릴 수 있고 상대적으로 소켓 수명이 긴 장점이 있다. 실리콘 고무 타입 소켓은 실리콘 고무 내부에 마이크로 볼을 위치시킨 형태로 개발되었으며, 단거리 고주파 적용 분야에서 비교적 좋은 결과를 보여주고 있고 테스트중 발생될 수 있는 칩의 손상을 최소화할 수 있는 장점이 있다.

최근 들어 나노기술의 발전으로 종래의 회로 설계 보다 더욱 더 고집적의 칩 제작이 기능해지면서 테스트 소켓 역시 상대적으로 높은 열 집중도와 전력 소비에 대한 대응이 필요한 실정이다. 즉, 테스트 소켓 역시 우수한 열적 내구성과 고전류등에 대응 가능한 소켓의 적용이 필요할 것이다.

본 연구에서는 분말 야금 공정을 통하여 고방열 금속 절연 소재를 제조하고 이를 기반으로 한 차세대 고성능 반도체 테스트용 소켓을 제작하였다. 특히 제조된 금속절연천이소재는 표면저항 제어가 가능하여 다양한 소재 부품으로 응용이 가능할 것으로 기대된다.

■ 주요 경력

▷ ㈜엔지엠 (Next Generation Materials Co., Ltd.) 대표이사
▷ 부경대학교 신소재시스템공학과 교수
▷ 스위스연방재료과학기술연구소 과학자
▷ 한국생산기술연구원 선임연구원
▷ 프랑스국립과학원 포스터 닥터
▷ 일본 Tohoku University 박사

■ 주요 대외 활동

▷(현)경사기능재료 국제자문위원 (IACFGM)
▷(현)일본산업총합기술연구소(AIST) 비상임연구원
▷(현)대한금속재료학회 복합재료분과위원
▷(현)한국복합재료학회 사업이사
▷(현)한국탄소학회 종신회원


Lunch and EXPO

Enjoy the delicious hot buffet lunch and networking time. Then take the time to explore the TestConX EXPO. There will be many great exhibits to connect electronic test professionals to solutions. You will be certain to see something new or meet someone new. As attendees to TestConX know, there is always excellent food, drinks, and time for attendees to network with exhibitors! TestConX EXPO will open at 12:15 and will remain open throughout the afternoon until 18:00


“The Semiconductor Packaging Market from a Historical Perspective”
장지훈 JiHoon Jang
Gadgetseoul Media
JiHoon Jang

고도의 분업체계. 반도체 시장의 운영 메커니즘이 만들어져 온 과정을 주목하고, 패키징 시장의 관전 포인트들을 짚어본다.

시장 최유력 기업들의 동향을 중심으로 어드밴드스 패키징 시장 현황을 정리하고, 이종교합으로 향해가는 반도체 플랫폼의 진화 양상과 장기적인 시사점을 고찰해보는 시간.

We will concentrate upon the process of creating the operating mechanism of the semiconductor market and touch upon major aspects in the packaging market. We will summarize the current status of the advanced packaging market, with a focus on the trends of the leading companies in the market. This is a time to contemplate the evolving trends of semiconductor platforms heading towards Heterogeneous-integration and their long-term implications.

Session 3

“Performance Evaluation: T033 vs Conductive Elastomer”
Frank "Dexian" Liu
Smiths Interconnect
Mike Ramsey
Smiths Interconnect
Abstract - Biography (English)

Plastronics is now part of Smiths Interconnect. Plastronics had sought to use the T033 H-Pin in plastic as a replacement for elastomeric interconnects due to its 1mm test height. With the Smiths team, access to data on elastomers is available for review. The thought was to perform testing to a T033 interposer and compare the data and see how well the T033 interposer performs in FDR cycle data through long term cycling.

Data is available on two different elastomers we will call elastomer A and elastomer B. We will perform similar testing to The T033 H-Pins so we can do a comparison of FDR data. We are assuming all three sets of data will perform equally well initially, but the elastomeric should show major resistance increases as cycles continue due to elastomeric compression set. The T033 H-Pin interposer should also show increase in resistance as well, but only very slight as compared to the conductive elastomers. If this proves to be true, we will move on to comparing RF data and seeing if the T033 performance in this area is equally as good as the elastomers. RF data would be created by modeling first, then followed up by actual test results. We will get a comparison of how well the models work to real world data. We will also get a comparison of the T033 RF performance to the Elastomers. This paper will initially target the mechanical part of the testing, but we will follow up with the electrical data for a future presentation if all goes as expected.

Frank Liu graduated from Shandong University of Science and Technology in 2001, majoring in Mechanical design and manufacturing. He studied for his MBA in Tongji University in 2018. Frank Liu started working in Smiths Interconnect Suzhou in 2007, and now he is Engineering Manager for Semi test product development.

“Obstacles and Challenges on Economic SiC Power Burn-In Process”
Gabriel Tak
Gary Park
Rio Shin
Hans Bae
Abstract (English)

Since the development of electronic devices, the world has been undergoing rapid and efficient evolution. Among various fields, a crucial aspect currently facing us is "power semiconductors." SEMICS, as a global semiconductor manufacturing equipment company in Korea, we want to discuss the existing problems and explore potential alternatives within this realm.

Currently, many global power semiconductor chip manufacturers are striving to achieve the demanded level of quality while establishing efficient mass production systems. Our company, SEMICS has put considerable effort into contemplating the value we can provide to our customers and has been working on developing solutions that can meet all requirements. One of the outcomes we are proud of is an efficient and versatile solution for the Wafer Level Burn-In (WLBI) process, which is at least one of the challenges faced by engineers today.

This technology focuses on addressing the issues in the current WLBI process of SiC / GaN wafers and solving associated research tasks through SEMICS' unique approach. We believe you will understand how we can efficiently and accurately measure the status of die and generate valuable data to feedback front SiC wafer process for definitive improvement.


Break & Networking

Enjoy time to meet with the presenters and network while refreshments are served.

Session 4
New Frontiers

“New Path to Narrow Pitch (0.1mm) Burn-in Socket Solution”
YK Lee
Abstract (English)

Burn-in socket is made by assembling contact pins and housing either manually or automatically. The assembled burn-in socket is then mounted on a PCB by soldering or compression mount. However, current burn-in socket technology hits the wall at about 0.27mm pitch.

New burn-in socket technology is presented for small pitches, up to 0.10mm.

Path to smaller pitch:

Reducing the pitch beyond the present limit requires paradigm shift in the burn-in socket manufacturing process. Traditional burn-in sockets are assembled first with contacts and housing, before mounted to the PCB. For the new burn-in socket, contacts are first soldered to the PCB. Socket housing is then added.

Solder paste is applied to the contact surface before affixing the contact pin to the PCB. Laser bonding will then solder the contacts to the PCB.

Very small pitch can be achieved with this process. The process can be automated, reducing the socket defects and cost.

Benefits of the new burn-in socket solution:

Reduced defect & reduced waste. Traditional burn-in socket would have to be discarded if there is solder bridge (short circuit) or cold solder joint with the PCB during socket assembly. Attaching the contacts to the PCB before adding socket housing allows for pre-inspection and repair of solder bridge and cold solder. Final defect rate can approach zero with the new process.

Saving material. Separator plates are used in traditional burn-in socket, to reduce electrical shorts and ease manufacturability. The new burn-in socket can eliminate the separator plate, to reduce cost. Fast socket deployment. The new burn-in socket system allows new socket development without any high-cost die cast molding. Fast new socket development, without high fixed cost, is possible. A new socket can potentially be made in one day.

“Introduction of MEM pins and sockets with AAO mold for the next-generation chip and packages”
“AAO를 이용한 차세대 반도체 전후공정 검사의 프로브카드용 핵심 부품 소개”
Seongho Park
Point Engineering
Abstract (English)

As the increasing a requirement of artificial intelligence (AI) and a huge of data, the process chips, such as processor, memory, and integrated circuits (ICs), became a higher level of integration. And it has faced demand on enhanced specifications – a higher process speed, a more compact size, etc.

The probe needles for the wafer test and the socket for package test are challenge points to meet functions – more delicate design and faster data gathering speed between the package and the system board in the narrow pad pitches.

AAO (anodic aluminum oxide) is a ceramic material capable of precise anisotropic etching, which used as a mold for fabricating probe needles. By applying this new material to MEMS technology, precise shapes (e.g spring shapes) even with very narrow gaps can be manufactured vertically straight with desired thickness(~130um).

We would like to introduce new MEMS technology for fabricating precise metal parts such as fine-pitch wafer test probe needles and differentiated spring pins for package test which can respond to the demand for next generation semiconductor inspection.

“Schematic AI Extractor”
Siang Hui Kiu
See Tien "Angie" Ng
Zhe Jin Lee
Yen Ming Siaw
Abstract - Biography (English)

The presentation introduces Schematic AI Extractor and how it assists the reviewer in reviewing and mining the data from schematic file. A schematic file usually contains lots of interfaces such as audio, display, memory, and so on. For each interface, there are details such as vendor, part number, voltage, technology type, and so on to be extracted. The Schematic AI Extractor can reduce some of the manual labour from the reviewer. The Schematic AI Extractor provides automatic extraction along with AI to interpret the extracted data of the components. Next, the details will filter using a similarity checking character by character with a threshold value method and a master list that contains details of the components. Once everything is passed, will be exported to a custom Excel sheet used by the reviewer.

Dr. Angie See Tien Ng is an AI Principal Engineer from Intel, who is the pioneer for Cloud based Remote Debug (CBRD), and spearheaded AI Chat bot. She has been in Intel for 14 years and in the industry for 26 years. Her career includes AI, R&D electronics design, RF designer, FPGA IC characterization, Electrical Validation, Functional Safety etc. Angie is always passionate in innovation and is honoured with Distinguished Invention Award by Intel. She graduated from Campbell University with BEng in Microelectronics/Physics in 1997, obtained her Master in Engineering from Multimedia University in 2014 and completed her PHD doctorate from University Science Malaysia in 2021 in area of designing Cloud-based virtual learning & testing for industry.

Siaw Yen Ming is a Cloud Application Engineer from Intel who is leading the Intel Penang Site Developer Cloud and involved in various AI initiatives including the AI Virtual Chat Bot. He has been in Intel for 8 years and in the industry for 10 years. (Motorola, Intel). His career includes Technical Support, Design & Electrical Validation, Firmware Validation and Software Development. He is graduated from University of Bradford UK with BEng in Electrical and Electronics Engineering in 2013.


Lucky Draw

Door prizes for randomly selected attendees
(Must be present to win / void where prohibited)


TestConX EXPO Closes / Event Adjourns

For any questions about the event or sponsorship contact us at [javascript protected email address].

Program subject to change without notice