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BiTS is the world's premier workshop dedicated to providing a forum for the latest information about burn-in and test socketing, and related fields.
At BiTS you'll find a comprehensive technical program, exhibits of the latest products and services, and many opportunities to meet, network and explore ideas with other test and burn-in socketing professionals.

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2001

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COPYRIGHT NOTICE

The papers in this publication comprise the proceedings of the 2001 BiTS Workshop. They reflect the authors’ opinions and are reproduced as presented , without change. Their inclusion in this publication does not constitute an endorsement by the BiTS Workshop, the sponsors, BiTS Workshop LLC, or the authors.


There is NO copyright protection claimed by this publication or the authors. However, each presentation is the work of the authors and their respective companies: as such, it is strongly suggested that any use reflect proper acknowledgement to the appropriate source. Any questions regarding the use of any materials presented should be directed to the author/s or their companies.


All photographs on this page are copyrighted by BiTS Workshop LLC. The BiTS logo and ‘Burn-in & Test Socket Workshop’ are trademarks of BiTS Workshop LLC.

Background

The second annual Burn-in and Test Socket (BiTS) workshop was sponsored by the Test Technology Technical Council of the IEEE Computer Society. BiTS is the only IEEE sponsored workshop dedicated to providing a forum for the latest information about the socket industry.

Technical Program

20 presentations, covering a range of important socketing topics, were delivered by suppliers and users. The presentations were organized into 8 sessions: four sessions on Monday, 2 on Tuesday and 2 on Wednesday. At registration, attendees received the Proceedings, which contain all of the presentations.

 

BiTS 2001 Expo (Supplier Displays)

New at BiTS this year were Supplier Displays. 22 suppliers displayed their products during breaks in the technical program.

Click HERE for a list of exhibitors.

BiTS 2001 Attendees

BiTS 2001 brought 198 participants from around the world representing end users and suppliers of sockets, boards, burn-in systems, handlers, packages and other related equipment, materials and services.

BiTS 2001 Organizing Committee
(front): Rafiq Hussain (AMD), Maddie Harwood (IEEE), Ariane Loranger (Loranger International), Joseph Riggs (Agere), John Ambrosini (Enplas-Tesco), Valts Treibergs (ECT)
(back): Alex Owen (WELLS-CTI), Owen Prillaman (Yamaichi), Fred Taber (IBM), Clay Carpenter (Intel), Paul Boyce (Motorola), not pictured: Wray Johnson (Texas Instruments)

 

BiTS 2001 Press

BiTS 2001 TECHNICAL PROGRAM

Sunday, March 4, 2001

8:30PM – Panel Discussion

"BROAD PACKAGE SPECIFICATIONS: AND THE SOCKET IS EXPECTED TO ALWAYS WORK?"

Moderator: Fred Taber IBM Microelectronics

Panel Members: Michael S. Carroll (Intel),   Jack Courtney (IBM Microelectronics),  Ed Craig (Texas Instruments), Tim Dowdle (Synergetix),  Michael Egloff (AMD), David Pfaff (Plastronics)

Monday, March 5, 2001

BiTS 2001 Welcome - Fred Taber

2001welcome.pdf pdficonsmall.gif (153 bytes) (614 KB)

8:30AM – Burn-in: Product Trends and Manufacturing Challenges

To get things rolling, this opening session covered a bit of history, where we are today and an outlook into the future for burn-in socketing. The challenges of cost, reliability, power, thermal management, and package proliferation, among others, were discussed.

  • "Facing The Power Of The Future - High End Burn-in Directions And Trends"
    Marc Knox, IBM Microelectronics
  • "Burn-in Of Memory Devices - A Look At The Past, Present And Future Of Memory Packaging And Interconnect Systems"
    Daniel Cram, Micron Technology
  • "Areas Of Conflict And Bottlenecks"
    Joseph J. Riggs,  Lucent-Bell Labs - Agere Systems

2001s1.pdf pdficonsmall.gif (153 bytes) (323 KB)

10:30AM – Directions in Test Socketing

Trends in packaging, performance and cost management are leading to innovative approaches to test processes, test socket hardware and broader applications for given sockets. This session's presenters provided a glimpse into these trends and offer their thoughts, analyses and conclusions.

  • "Spring Contact Probes For IC Device Testing"
    Tim Dowdle, Synergetix
  • "Strip Test - Evolution, Considerations And Resources"
    Brian Crisp,  Everett Charles Technologies
  • "Lowering The Cost Of High Performance Test And Burn-in"
    James Rathburn, Gryphics, Inc.

2001s2.pdf pdficonsmall.gif (153 bytes) (1.4 MB)

1:00PM –Electrical and Mechanical Modeling and Analysis

This afternoon's four paper session was a follow-on to last year's highly acclaimed Characterization and Evaluation session: 2 papers won awards and it had the highest number of hits on the BiTS website. Experiences, techniques and tools for mechanical and electrical modeling, analysis, evaluation and testing were discussed. Topics included a range of work on socket contacts, alignment and RF response.

  • "Review Of Burn-in Socket Contact Platings"
    Thomas A. Bradley, Agere Systems
  • "A Finite Element Analysis Of Solder Balls On A BGA Package In Sockets During Burn-in"
    Alfred Sugarman, Ariane Loranger,  Loranger International Corp.
  • "SPICE Model Extraction From S Parameter Data For Test Contactors"
    Valts Treibergs,  Everett Charles Technologies
  • "Least Squares Analysis Of Composite True Position Specification"
    Alex Owen, Wells-CTI

2001s3.pdf pdficonsmall.gif (153 bytes) (1.0 MB)

3:30PM – Burn-in Board Design

Burn-in board design considerations and requirements are increasingly more complex. Several users addressed the challenges of increased power demands, maintaining signal integrity at higher frequencies, maximizing board real estate utilization and improving productivity and throughput.

  • "High Power BIB Power Plane Design And Decoupling Simulation"
    Zamel Jaafar, Anthony Wong Peter Ngaa,  Intel
  • "Cost Effective Burn-in Board Design"
    Frank W. Jurasek, Ralph J. Bernardini, James M. Brown, IBM Microelectronics
  • "High Speed & High Power Burn-in Board Design"
    Hon-Lee Kon, Cher-Shyong Low,  Intel (Presented by Zamel Jaafar, Intel)

2001s4.pdf pdficonsmall.gif (153 bytes) (963 KB)

8:00PM – Keynote Speaker

"WAFER LEVEL PARADIGM FOR BURN-IN AND TEST?"

Dr. Thomas Di Stefano,  President and CEO Decision Track, LLC

2001keynote.pdf pdficonsmall.gif (153 bytes) (1.1 MB)

Tuesday, March 6, 2001

8:00AM – Methods in Burn-in and Test

Mix advanced burn-in hardware with new techniques in test methodology during burn-in and you'll have a picture of this session. Discussions were about systems to address high power and thermal requirements and techniques to improve throughput and lower costs.

  • "Active Thermal Control During Burn-in"
    Ken Heiman, Micro Control Company
  • "Embedded Test Solution For Burn-in"

    Charles McDonald (Presented by Steve Pateras), LogicVision, Inc.
  • "Next Generation Burn-in & Test System For Athlon Microprocessors: 'Hybrid Burn-in'"

    Mark Miller, Advanced Micro Devices

2001s5.pdf pdficonsmall.gif (153 bytes) (2.4 MB)

10:30AM –Thermal Management Approaches

Solving the rapidly growing thermal management demands, during test and burn-in of today's higher powered devices, is essential. This session presented three papers covering theory, modeling, analysis, methods and practical solutions for test and burn-in processes and environments.

  • "Dynamic Junction Temperature Control For Lidded C4 Packages"
    Joe Hovendon, Schlumberger
  • "Approaches To Thermal Management Of High Power Devices"
    Paul Nesrsta, Reliability Incorporated
  • "Dixie Chips - 'Too Hot To Handle'"
    Jim Ostendorf, Dynavision

2001s6.pdf pdficonsmall.gif (153 bytes) (812 KB)

Wednesday, March 7, 2001

8:00AM – Advancements in Socket Products

We learn about some new socket products. The medley of papers in this session addressed a variety of challenges socket engineers face and offered solutions.

  • "PASS Chip"
    Min Cho, Inabata America Corporation
  • "Evaluating Elastomer For High Density BGA Socket"
    Ila Pal,  Ironwood Electronics, Inc.
  • "Low Cost Thermal Management Using Compliant Thermal Interface Materials"

    Nancy Dean, Kenichiro Fukuyama, Honeywell Electronic Materials

2001s7.pdf pdficonsmall.gif (153 bytes) (1.4 MB)

10:30AM – Test and Burn-in at the Wafer Level

The movement to wafer level test and burn-in is growing. Will this affect socketing? How? What are the obstacles? What solutions are out there? Our three presenters discussed the progress on wafer level work and the challenges.

  • "Wafer Level Burn-in And Test"
    Teresa McKenzie, Walid Ballouli, John Stroupe,  Motorola & Stroupe Consulting
  • "Some Scenarios On Wafer-Level Test & Burn-in"
    Robert Y. Million,  Yamaichi Electronics USA, Inc.

2001s8.pdf pdficonsmall.gif (153 bytes) (2.0 MB)

 

IEEE CS

BiTS2001

Original Sponsoring Organization

IEEE
 

Page last modified 12/23/09

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