
Sunday March 1, 2026
There will be breaks including refreshments to provide networking time for Tutorial attendees.
Please note: attendance at the tutorial will be limited. Please sign-up early to not miss out!
1:00 to 4:30 p

We are in the era of applications using different intellectual property (IP), different die geometries, and with more than one known good die (KGD) in a single package. Business units exercise the option of integrating different IPs from different IP providers to achieve the desired performance, functional technology, and cost as they are no longer limited to in-house IP. This creates the need to merge IPs with differing speed and power performance requirements. Test and product engineers are tasked with the delicate integration of complex devices under test (DUT), interposers, printed circuit boards, and support circuits. Along with the challenge of IP protection and security.
Who should attend this tutorial?
- Test and product engineers involved with or work on complex DUT and associated hardware
- Hardware providers such as interposers (e.g. test socket), printed circuit board designers, and support board circuit providers
- Providers of test and measurement such as Automated Test Equipment, Vector Network Analyzers, etc.
Includes Networking Break
5:30 p
Welcome Reception
If this is your twenty-seventh time attending TestConX, only your first, or somewhere in-between you will feel welcomed at the opening reception by friends old and new.
6:30 p
Dinner
The first of many excellent meals awaits as you get to network with other industry professionals. This is a great time to catch up with old colleagues or start meeting new friends.
7:30 p
9:00 p
Adjourn
Program subject to change without notice.