Suwon, South Korea - October 27, 2026
141-36 Botong-ri, Jeongnam-myeon, Hwaseong-si,
Gyeonggi-do, South Korea
TestConX, over the course of its twenty-seven-year history, has established itself as the preeminent event for test consumables, test cell integration, and test operations. The program scope includes packaged semiconductor “final” test, burn-in, system level test, and beyond to encompass all practical aspects of electronics testing such as validation, advanced packaging testing, module test, and finished product test.
Please join us for our 4th annual TestConX Korea! Don’t miss this opportunity to be part of TestConX as we connect a larger community of test professionals and to participate in this excellent event!
Tuesday October 27, 2026
9:00
9:15
“동축/비동축 구조의 엘라스토머 테스트 소켓의 성능 비교”
Abstract - Biography (English)
High-speed semiconductor testing increasingly requires test sockets with improved signal integrity and electrical performance.
This study compares the electrical characteristics of coaxial and non-coaxial elastomer test socket structures for high-speed test applications.
The coaxial structure provides a controlled signal and ground configuration, enabling improved impedance control and reduced electromagnetic coupling between adjacent signal paths.
Electrical performance is evaluated in terms of insertion loss, return loss, crosstalk, and impedance characteristics over a wide frequency range.
The results demonstrate the impact of socket interconnect architecture on high-frequency signal transmission and identify the performance advantages and design considerations of the coaxial configuration.
These findings provide practical guidance for test socket design targeting next-generation high-speed and high-frequency semiconductor devices.
Jimin Song is currently pursuing the M.S. degree in Semiconductor Engineering at Kyung Hee University, South Korea. His research focuses on electrical validation and signal integrity analysis of high-speed chiplet interconnects and advanced semiconductor packages.
초록 - 전기 (Korean)
고속 반도체 테스트 환경에서는 우수한 신호 무결성(Signal Integrity)과 전기적 특성을 갖는 테스트 소켓의 중요성이 점차 증가하고 있다.
본 연구에서는 고속 테스트 응용을 위한 동축(Coaxial) 및 비동축(Non-coaxial) 엘라스토머 테스트 소켓 구조의 전기적 특성을 비교 분석하였다.
동축 구조는 신호선과 접지의 배치를 제어함으로써 안정적인 임피던스 특성을 구현하고 인접 신호 간 전자기적 결합을 감소시킬 수 있다.
두 구조의 전기적 성능을 삽입손실(Insertion Loss), 반사손실(Return Loss), 누화(Crosstalk) 및 임피던스 특성을 중심으로 광대역 주파수 영역에서 평가하였다.
이를 통해 테스트 소켓의 인터커넥트 구조가 고주파 신호 전송 특성에 미치는 영향을 분석하고, 동축 구조가 제공하는 전기적 성능상의 이점과 주요 설계 고려사항을 제시하였다.
본 연구 결과는 차세대 고속·고주파 반도체 테스트를 위한 엘라스토머 테스트 소켓 설계 및 최적화에 실질적인 가이드라인을 제공할 수 있다.
본 발표자 송지민 학생은 현재 경희대학교 반도체공학과 석사과정에 재학 중이다. 주요 연구 분야는 고속 Chiplet Interconnect와 첨단 반도체 패키지의 전기적 검증 및 Signal Integrity 분석이다.
Abstract - Biography (English)
As large packages such as HBM see wider adoption, the metal trays used in high-temperature reflow processes for reliability testing can cause thermal damage to transfer components, such as the equipment's internal conveyor belts, creating a need for tray temperature-reduction design technology. This study proposes an optimal design that reduces the tray's heat capacity through lightweight design, thereby lowering the post-reflow tray temperature. The approach is developed and validated through finite element analysis (FEA) and prototype evaluation.
Gyu-Yeol Kim received his B.S. degree in Electrical Engineering from Kyunghee University, Suwon, Korea, in 2000, and his M.S. and Ph.D. degrees in Electrical Engineering from Sungkyunkwan University, Suwon, Korea, in 2008 and 2017, respectively. His current research interests include the design of memory package boards, sockets, and probe cards. Since 2000, he has been with Samsung Electronics, where he is a Principal Engineer of the EDS Test Technology Group.
摘要 (Chinese)
신뢰성 검증 고온 리플로우 공정용 HBM 메탈 트레이의 경량화 설계 최적화
초록 - 전기 (Korean)
HBM과 같은 대형 패키지의 적용 확대에 따라 신뢰성 평가를 위한 고온 리플로우 공정에 사용되는 메탈 트레이를 이용한 장비 내부 반송 벨트 등 이송 부품의 열손상을 유발할 수 있어 트레이 온도 저감 설계 기술이 요구된다. 본 연구에서는 메탈 트레이의 경량화를 통해 열용량을 감소시켜 리플로우 이후 트레이 온도를 낮출 수 있도록 유한요소해석과 시제품 평가를 통한 최적 설계 방안을 제안한다.
경희대학교 전자공학과(2000), 성균관대학교 전기전자공학과 석사(2008), 박사(2017), 2000년 2월 ~ 현재: 삼성전자(메모리) 수석연구원. 관심분야: package test board, socket, probe card, memory test.
10:15
Break & Networking
Enjoy time to meet with the presenters and network while refreshments are served.10:45
Prof. Donghwan Ahn is presently a professor in the School of Materials Science and Engineering at Kookmin University, Seoul, Korea. Prior to joining Kookmin University, he was a Senior Research Engineer and a team leader of Advanced Silicon Photonics and Electronics Lab at Samsung Electronics U.S. R&D Center (SAIT-USA). He received B.S. and M.S. degrees in materials science and engineering from Seoul National University, South Korea, in 1996 and 2000, respectively.
He earned his Ph.D. degree from Massachusetts Institute of Technology (MIT) in 2007, under the guidance of Prof. Lionel C. Kimerling. In his Ph.D. dissertation entitled “Intra-chip Clock Signal Distribution via Si-based Optical Interconnect”, he pioneered an H-tree waveguide network and demonstrated the world’s first waveguide-integrated germanium photodetector, which is now widely adopted in optical engine chiplets for Co-Package Optics (CPO). Prior to joining Samsung, he was an NSF/ASEE Research Fellow at Bell Laboratories, Alcatel-Lucent, where he conducted research on silicon CMOS-compatible photonic devices in the Advanced Photonic Integration group, and a Senior Research Scientist at Astrowatt Inc., a solar cell start-up company in Austin, Texas. His current research interests include germanium-based photonic and electronic devices, optical interconnect and packaging for AI and high-performance computing, and photonic integrated circuits for quantum computing chip.
11:45
Lunch & EXPO
Enjoy the delicious hot buffet lunch and networking time. Then take the time to explore the TestConX EXPO. There will be many great exhibits to connect electronic test professionals to solutions. You will be certain to see something new or meet someone new. As attendees to TestConX know, there is always excellent food, drinks, and time for attendees to network with exhibitors! TestConX EXPO will open at 11:45 and will remain open throughout the afternoon until 18:0013:30
가젯서울 미디어의 장지훈 대표는 한국외국어대학교를 졸업한 후 한화그룹 공채로 커리어를 시작했다. 전략/기획팀에서 근무하며 IT 분야의 머천다이저로 브랜드와 상품을 전개하였다. 이후 경제지 이코노미 조선의 IT전문 칼럼니스트로 업계의 시황과 선행기술들에 대한 깊이 있는 인사이트를 공유해왔다. 현재는 유튜브 채널 가젯서울을 통해 상품과 브랜드, 기술과 시황을 균형감있게 조망하는 영상 칼럼을 제공하고 있다.
Jihoon Jang, the CEO of Gadgetseoul Media, developed and narrates the highly informative and popular Gadgetseoul YouTube channel focused on semiconductors and technology. Prior to which he was an Information Technology columnist for Economy Chosun. He started his career at Hanwha group as an IT/Tech Merchandiser, managing and promoting many brands and products on the Strategy/Planning team after completing his studies at Hankuk University of Foreign Studies.
14:45
Posters & EXPO
Enjoy time to meet with the presenters and network while refreshments are served.Abstract (English)
Managing Automated Test Equipment (ATE) test programs using traditional methods like shared drives created significant challenges for our team. It was often difficult to track changes across multiple files and versions, leading to confusion and potential errors. Coordinating parallel development tasks was complicated, especially when working with distributed teams and external vendors responsible for creating and debugging test programs. These issues frequently caused communication breakdowns, inefficient workflows, prolonged debugging cycles, and delayed product releases.
To tackle these challenges, we transitioned our version control process to GitHub, adopting a structured workflow with branches and tagged releases. GitHub, widely recognized and commonly used in software development, gave us a transparent and straightforward approach to organizing and managing test program versions. We developed consistent branching strategies aligned with our development phases and regularly used tags to indicate stable releases and important milestones. This allowed us to manage multiple concurrent test code versions effectively.
By streamlining our communication through clearly documented commits and leveraging GitHub’s collaborative tools, we reduced the need for frequent coordination meetings with external vendors. This significantly enhanced our efficiency, resulting in development timelines improving by up to 40%.
Since moving to GitHub, we’ve experienced notable productivity improvements. It has become significantly easier to handle multiple projects simultaneously and maintain accurate and detailed records of changes. Debugging and validation processes have become faster due to enhanced visibility into code changes, allowing us to quickly pinpoint and resolve issues. Our release processes have also become more reliable, with preparation times reduced from several days to just a few hours.
One of the greatest advantages has been the improvement in collaboration, both within our internal engineering teams and with external vendor partners. Everyone now benefits from clear visibility into ongoing development activities and quick access to the latest test program versions. This improved communication helps us rapidly adapt to design modifications, customer feedback, and changing testing requirements, which is critical in today’s dynamic semiconductor environment. Additionally, using GitHub as our collaboration platform enabled seamless, around-the-clock development in partnership with international teams. By exchanging and updating ASCII files directly on GitHub, we eliminated delays from downloading or transferring files, significantly speeding up our joint workflow.
Overall, integrating GitHub into our ATE test program management has greatly improved our workflow efficiency, strengthened collaboration, enhanced traceability, and significantly boosted productivity. This strategic shift has streamlined our current operations and better positioned us to support future advancements in semiconductor test engineering.
Abstract (English)
Testing of 20-bit digital-to-analog converters (DACs) is typically performed using automated test equipment, which is costly and requires complex handler configuration. As an alternative, the rack-and-stack method facilitates testing without such expensive equipment by employing a digital pattern generator to supply the required digital codes. Comprehensive evaluation of a 20-bit DAC necessitates 1,048,576 digital codes. Although this method increases test duration and reduces product margin, this study presents a methodology utilizing a desktop rack-and-stack system to generate digital patterns, apply them to a 20-bit DAC, and measure the resulting output voltage.
The output voltage is measured with an integrated oscilloscope, and a Python script is implemented to assess differential nonlinearity (DNL), integral nonlinearity (INL), offset error, and gain error. The same rack-and-stack benchtop system is used to describe the methodology for measuring power supply rejection ratio (PSRR). The measurement system includes a network analyzer capable of sweeping the ripple frequency in under thirty minutes and generating a PSRR report. Software algorithms for PSRR measurement are detailed, and the assessment of AC characteristics of a 20-bit DAC using the rack-and-stack test system is also addressed.
The methodology to reduce ripple caused by di/dt during power system activation is discussed. Additionally, the use of a Faraday cage is examined to minimize radio frequency interference during the measurement of DC and AC parameters of digital-to-analog converters.
Abstract (English)
Accurate testing of 12-, 16-, and 20-bit Digital-to-Analog Converters requires a precision voltage supply to measure differential non-linearity, integral non-linearity, gain error, and offset error. This paper details the delivery of precise on-board analog, digital, and reference voltages using a highly efficient 95% buck-boost converter.
The described DC-DC converter features an enable pin for power sequencing, which can be controlled via a switch or a microcontroller's general-purpose input/output (GPIO) pin. Minor voltage drops may result from the board's inherent IR drop. The methodology uses an 8-bit Digital-to-Analog Converter (DAC) in the feedback path to ensure precise voltage delivery to the device under test. In contrast to conventional DC-DC converters that rely on feedback resistors, integrating an 8-bit DAC simplifies voltage control.
Further technical details are presented in subsequent sections. Within the graphical user interface (GUI), the 8-bit DAC control bit should be set before applying a precise voltage to the integrated circuit pins. The DC-DC converter can deliver up to 3.87 V at 5 A and support up to 15 converters on a single test board, offering a cost-effective solution.
15:45
“诊断模拟引脚电子器件中由SOA引起的老化漂移：对AI与HPC测试的启示”
Abstract - Biography (English)
Silent Data Corruption (SDC) and post-deployment hardware faults have emerged as significant reliability concerns for hyperscale AI and HPC infrastructure, with recent industry reports from Google, Meta, and the Open Compute Project (OCP) highlighting defects that pass manufacturing test but only manifest under specific bias conditions or after extended operation. The published case studies are predominantly digital. In this study, we examine the same failure class in an analog Automated Test Equipment (ATE) pin electronics ASIC, devices that perform final test on AI and HPC silicon.
A customer reported progressive VCOM threshold drift on a 256-channel application, affecting approximately 50% of channels and continuing past -900 mV with no observable stabilization. All affected devices had passed final test before production. Failing devices were inspected, and results from initial visual inspection, ATE re-test, and emission microscopy were inconclusive. Bench characterization across 50 devices spanning multiple lots and date codes confirmed that the drift was reproducible and exhibited strong dependence on register configuration and operating temperature but evaded standard production screening due to its time-dependent nature.
Failure analysis techniques such as Focused Ion Beam (FIB) produced misleading initial results. Severing a capacitor and diode in the comparator path arrested the drift, which initially appeared to identify the offending components. A subsequent control FIB cutting non-functional metal also halted the drift, demonstrating that the FIB process itself was perturbing the measurement rather than the targeted devices. This sensitivity to invasive characterization is a notable hazard for this defect class and constrains the design of subsequent debug experiments.
Root cause was traced to Safe Operating Area (SOA) violations within the analog comparator. Floating-node conditions in one register state and an over-stressed gain-stage VGS in another subjected gate oxides to chronic overstress, accelerating Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI). Pre-silicon simulation did not flag the floating-node case due to the initial conditions the simulator applies, preventing the very condition responsible. Final test could not screen for the effect because the resulting offset is sub-microvolt at t = 0 and accumulates only after days of biased operation.
This case study underscores the importance of integrating aging-aware design verification with adaptive test strategies for analog devices intended for long-deployment applications. The presentation walks through the diagnostic flow, the validated workaround shipped to the customer during silicon respin development, and the design corrections incorporated in successor revisions. We conclude with recommendations for screening long-latency, bias-dependent drift in the analog devices on which AI and HPC test programs increasingly depend, including SOA analysis during pre-silicon verification, extended-stress characterization protocols, and closer coordination between design verification and production test engineering teams.
Hailin is an Applications Engineer at ElevATE Semiconductor with a strong engineering background and a passion for innovation. He holds a degree from the University of Toronto, where he also engaged in academic research collaborations, and has professional experience spanning software development and mixed-signal engineering.
Dedicated to tackling complex technical challenges and fostering opportunities for students, Hailin is committed to advancing the field of semiconductor test while inspiring the next generation of professionals. He is currently pursuing a master’s degree at UC Berkeley, focusing on applying statistical models and data science principles to enhance test engineering.
摘要 - 简介 (Chinese)
静默数据损坏（SDC）与部署后硬件故障已成为超大规模AI与HPC基础设施可靠性的重要议题，Google、Meta及开放计算项目（OCP）近期报告均指出，部分缺陷器件可通过出厂测试，却仅在特定偏置条件或长期运行后才会显现。已发表案例以数字器件为主，本研究则针对同类故障机制在模拟自动测试设备（ATE）引脚电子专用集成电路（ASIC）中的表现进行分析。
某客户报告在一款256通道应用中出现渐进性VCOM阈值漂移，约50%通道受影响，且无收敛迹象，所有器件均已通过出厂测试。初步目视检查、ATE复测及发射显微镜检测均无法定位问题。跨批次台架表征证实该漂移可重复，且与寄存器配置及工作温度密切相关，因其时间依赖特性而未被标准量产筛选捕获。
聚焦离子束（FIB）分析初期给出误导性结果：切断比较器路径中的特定元件后漂移即停止，但后续对照实验显示，切割无功能金属走线同样能中止漂移，证明是FIB加工过程本身干扰了测量。这一现象揭示了该类缺陷对侵入式表征手段的敏感性，也限制了后续调试实验的设计。
根本原因被追溯至模拟比较器内部的安全工作区（SOA）违规：特定寄存器状态下的悬空节点及增益级过应力，使栅氧化层长期承受过应力，加速了热载流子注入（HCI）与偏置温度不稳定性（BTI）效应。由于仿真初始条件规避了悬空节点状态，前硅仿真未能捕捉该问题；而由此产生的偏移在t=0时仅为亚微伏级，须经数日偏置运行方逐渐显现，因而也无法被最终测试筛出。
本案例研究表明，针对长期部署应用的模拟器件，需将老化感知设计验证与自适应测试策略相结合。报告将介绍诊断流程、提供给客户的验证性临时方案，以及后续版本中的设计改进，并就前硅SOA分析、扩展应力表征及设计验证与量产测试团队协作提出建议，以筛查AI与HPC测试所依赖的模拟器件中长潜伏期、偏置依赖性漂移问题。
Hailin 是 ElevATE Semiconductor 的应用工程师，具备扎实的工程背景并对创新充满热情。他毕业于多伦多大学，并参与了多项学术研究合作，职业经历涵盖软件开发与混合信号工程。
Hailin 致力于解决复杂的技术挑战并为学生创造机会，专注于推动半导体测试领域的发展，同时激励下一代工程专业人才。他目前正在加州大学伯克利分校攻读硕士学位，研究重点是运用统计模型和数据科学原理提升测试工程水平。
“테스트 플로어에서 씽킹 플로어로: 반도체 테스트의 에이전트 기반 미래”
Abstract - Biography (English)
Abstract
Semiconductor test today operates as a sequence of disconnected stages — EDA, wafer sort, final test, system-level test, reliability, and field — each with its own tools, its own datalog format, and its own engineering teams. The result is well understood across the industry: an SLT escape rarely traces cleanly back to a sort signature, characterization data is reconstructed by hand for every yield investigation, and the engineer's most expensive task is not running tests but stitching context together across stages.
This talk proposes a different shape for the next decade of test: a thinking test floor in which the tester becomes a deterministic execution engine, the IDE becomes optional, and a fleet of discipline-specialized AI agents — Test, Thermal, Characterization, Yield, Reliability, SLT, Application Engineering — operates above a unified analytics platform on a common Device Log that follows each die from EDA through field return.
We will outline a vendor-neutral, three-layer architecture that makes this possible:
- An Agent Fleet the engineer steers at the level of intent rather than clicks.
- An Agentic Control Plane that translates intent into measurement operations through domain-shaped tools and enforces hardware-safety envelopes structurally.
- A headless execution layer with a stable contract for ingesting machine-authored, signed, version-controlled test programs.
Binding the three layers together is a Unified Device Log — a schemaed, append-only, customer-owned record keyed to each device's lifelong identity — which turns cross-stage investigation from a project into a query.
We will also examine the corresponding shift toward simulation-led test development, in which agents iterate against virtual testers and digital-twin device models long before silicon is touched, and discuss what this means for tooling, IP boundaries, customer trust, and the engineering organizations that operate the test floor.
What Attendees Will Take Away
- A concrete architectural picture of how AI agents move from "smarter autocomplete inside the IDE" to first-class operators of the test floor across every stage from EDA to SLT.
- A practical framing of the Unified Device Log as the spine that makes cross-stage investigation tractable — including schema, identity propagation, and the customer IP boundary.
- A clear distinction between an agent that has hands (action surface), knowledge (domain-shaped tools), and memory (the device log) — and why all three are required for autonomy.
- Why simulation and digital-twin-led development is the natural next step once test programs become machine-authored artifacts rather than hand-edited files.
- An honest discussion of the open problems: hardware safety on live silicon, customer-IP protection, agent guardrails, and the organizational changes that come with intent-driven testing.
Audience and Relevance
Test engineers, characterization engineers, yield and reliability leads, ATE platform architects, EDA and SLT practitioners, and engineering and executive leadership looking to catch the next stage of the semiconductor test era.
Particularly relevant for organizations facing the cost of cross-stage data fragmentation and looking for a credible path from today's IDE-centric workflows to AI-native, intent-driven test operations.
Mykola Zakharchuk is Product Owner at Advantest with ten years of experience in semiconductor test. He works at the intersection of generative AI and automated test, focusing on how large language models, agent frameworks, and open protocols such as the Model Context Protocol are reshaping the way test programs are authored, executed, and debugged.
His current work centers on the long-term vision for an agentic test platform spanning EDA through SLT, with a common analytics layer and a Unified Device Log as its spine. He speaks regularly on the future of AI in semiconductor test.
초록 - 전기 (Korean)
초록
오늘날 반도체 테스트는 EDA, 웨이퍼 소트, 파이널 테스트, 시스템 레벨 테스트(SLT), 신뢰성, 필드에 이르기까지 서로 단절된 단계들의 연속으로 운영되며, 각 단계는 고유의 툴과 데이터로그 포맷, 그리고 별도의 엔지니어링 팀을 가지고 있습니다.
그 결과는 업계에 잘 알려져 있습니다. SLT 단계의 불량(escape)이 소트 시그니처로 깔끔하게 추적되는 경우는 드물고, 특성화(characterization) 데이터는 수율 분석마다 수작업으로 재구성되며, 엔지니어의 가장 값비싼 업무는 테스트 실행 자체가 아니라 여러 단계에 걸친 문맥을 이어 붙이는 일입니다.
본 발표는 향후 10년의 테스트에 대해 다른 형태를 제안합니다. 테스터는 결정론적(deterministic) 실행 엔진이 되고, IDE는 선택 사항이 되며, 분야별로 특화된 AI 에이전트 집단 — 테스트, 열(Thermal), 특성화, 수율, 신뢰성, SLT, 애플리케이션 엔지니어링 — 이 통합 분석 플랫폼 위에서, EDA부터 필드 반품까지 각 다이(die)를 따라다니는 공통 디바이스 로그(Device Log)를 기반으로 동작하는 ‘사고하는 테스트 플로어(thinking test floor)’입니다.
이를 가능하게 하는 벤더 중립적(vendor-neutral) 3계층 아키텍처를 소개합니다.
- 엔지니어가 클릭이 아니라 의도(intent) 수준에서 조종하는 에이전트 플릿(Agent Fleet).
- 의도를 도메인에 맞춰진 툴을 통해 측정 동작으로 변환하고 하드웨어 안전 범위(safety envelope)를 구조적으로 강제하는 에이전틱 컨트롤 플레인(Agentic Control Plane).
- 기계가 작성하고 서명·버전 관리된 테스트 프로그램을 수용하는 안정적 계약(contract)을 갖춘 헤드리스(headless) 실행 계층.
이 세 계층을 하나로 묶는 것은 통합 디바이스 로그(Unified Device Log)로, 각 디바이스의 평생 식별자에 연결된 스키마 기반의 추가 전용(append-only)·고객 소유 기록이며, 단계 간 분석을 하나의 프로젝트에서 하나의 쿼리로 바꿔 놓습니다.
또한 실제 실리콘을 다루기 훨씬 전에 에이전트가 가상 테스터와 디지털 트윈 디바이스 모델을 대상으로 반복 개발을 수행하는 시뮬레이션 주도(simulation-led) 테스트 개발로의 전환을 살펴보고, 이것이 툴링, IP 경계, 고객 신뢰, 그리고 테스트 플로어를 운영하는 엔지니어링 조직에 어떤 의미를 갖는지 논의합니다.
미콜라 자하르추크(Mykola Zakharchuk)는 Advantest의 프로덕트 오너(Product Owner)로, 반도체 테스트 분야에서 10년의 경력을 보유하고 있습니다.
그는 생성형 AI와 자동 테스트의 접점에서, 대규모 언어 모델(LLM), 에이전트 프레임워크, 그리고 Model Context Protocol과 같은 개방형 프로토콜이 테스트 프로그램의 작성·실행·디버깅 방식을 어떻게 변화시키고 있는지에 주목하며 연구하고 있습니다.
현재는 EDA부터 SLT까지 아우르는 에이전트 기반 테스트 플랫폼과, 그 중심축이 되는 공통 분석 계층 및 통합 디바이스 로그(Unified Device Log)에 대한 장기 비전에 집중하고 있습니다.
그는 반도체 테스트 분야에서 AI의 미래에 대해 정기적으로 강연하고 있습니다.
Abstract (English)
This paper presents a hardware (HW) and software (SW) approach to Power Supply Rail Multi Switching on a Device Power Supply (DPS) using multiple voltage rails. Implemented with the Whitney DPS as a demonstration platform, the system selects the most efficient voltage rail based on output demand to reduce power loss, lower heat dissipation, and improve thermal performance. The design supports both hardware-based comparator logic and software-based digital control for flexible envelope-tracking operation.
The solution uses make-before-break rail switching, eFuse protection, buffered voltage sensing, and threshold-based control to maintain continuous operation during voltage transitions. Results from both hardware and software demonstrations at 200 mA, 500 mA, and up to 1 A show stable rail handoff and reliable output regulation across changing load conditions.
These results demonstrate that the proposed Envelope-Tracking Power Supply (ETPS) is an effective solution for improving power efficiency, thermal management, and system reliability in high-voltage DPS applications.
17:15
Lucky Draw
Door prizes for randomly selected attendees
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