Abstract

The Rank Margin Test (RMT) has been used to optimize the channels and Rx/Tx circuits between the Central Processing Unit (CPU) and Dynamic Random-Access Memory (DRAM). The RMT process is an unknown process; machine learning (ML) is applied to analyze the RMT data. Neural networks (NN) and their hyperparameters are optimized in this work to improve trainability.

Biography

Junyong Park received the B.S. degree from Sungkyunkwan University in 2014, and the Ph.D. degree from the Korea Advanced Institute of Science and Technology (KAIST) in 2019. He was with the DRAM design team at SK Hynix from 2019 to 2023, and joined the Missouri University of Science and Technology from 2023 to 2024. He was with Dankook University by 2025, and he is currently with Kyung Hee University as an assistant professor. His current research interests include statistical signal/power integrity for high-speed systems, next-generation packaging, and input/output buffer information specification with an algorithmic modeling interface.

초록

Rank Margin Tool (RMT)는 중앙처리장치(CPU)와 DRAM간 송/수신 회로 및 이들을 연결하는 고속 채널을 최적화하기 위해서 사용되고 있다. RMT 데이터는 분석이 힘들기 때문에, 기계 학습을 이용하여 RMT 데이터를 분석한다. 얼마나 학습이 잘 되는가(trainability)를 통해 인공신경망과 그의 하이퍼 파라미터들이 최적화된다.

약력

본 연구자는 2014년 성균관대학교에서 학사 학위를, 2019년 한국과학기술원(KAIST)에서 박사 학위를 받았다. 2019년부터 2023년까지 SK하이닉스 DRAM 설계팀에서 근무했으며, 2023년부터 2024년까지 미국 미주리 과학기술대학교(Missouri University of Science and Technology)에 재직했다. 2024년부터 2025년까지 단국대학교에서 근무했으며, 2025년 9월부로 경희대학교에서 조교수로 재직 중이다. 그의 주요 연구 분야는 고속 시스템의 통계적 신호·전력 무결성, 차세대 패키징, 알고리즘 모델링 인터페이스를 이용한 입출력 버퍼 정보 사양(IBIS) 등을 포함한다.

Abstract

The automotive industry's rapid evolution toward electrification and advanced driver assistance systems (ADAS) has dramatically increased demands for semiconductor components capable of withstanding extreme operating conditions while maintaining uncompromising reliability. This poster introduces Whitney, Elevate Semiconductor's innovative two-channel high voltage parametric measurement unit (PMU) System-on-a-Chip, designed specifically to address the rigorous testing requirements of high reliability automotive integrated circuits operating at voltages approaching up to 100V.

Modern electric vehicles incorporate power management systems operating at increasingly higher voltages, with 48V systems becoming standard and full EV powertrains utilizing voltages of 400-800V. This evolution necessitates test equipment capable of characterizing device performance across expanded voltage ranges while maintaining precise measurement accuracy. Whitney delivers this capability through its unique stackable architecture, achieving test voltages suitable for next-generation automotive applications while preserving 0.05% measurement accuracy.

Elevate Semiconductor's solution implements a floating DUT configuration where two Whitney ICs can be stacked, with each channel operating in Master Mode to regulate either positive or negative voltages relative to adjacent channels. This configuration enables comprehensive four-quadrant testing critical for automotive qualification procedures. The comprehensive integration of six 16-bit DACs per channel enables Whitney to simultaneously force voltage on one channel, force current while doing measure voltage or measure current, and perform window compare measurements—all essential functions for characterizing automotive-grade semiconductors. With SPI interface speeds up to 50MHz, the Whitney significantly reduces test time without compromising measurement integrity, addressing a critical challenge in high-volume automotive semiconductor production.

This poster will demonstrate how Elevate Semiconductor's Whitney platform enables automotive IC manufacturers to perform rigorous qualification testing of high voltage components while maintaining the throughput necessary for competitive manufacturing environments. We will present measurement data demonstrating how stacked Whitney configurations maintain measurement fidelity across extended voltage ranges, with particular emphasis for Automotive Semiconductor IC grade testing.

The culmination of these capabilities positions Whitney as an essential tool for qualifying the next generation of high reliability automotive semiconductors, ensuring they meet the exacting standards necessary for safe operation throughout their service lifetime in demanding automotive environments. As vehicle architecture continues evolving toward higher voltage platforms, Elevate Semiconductor's solution provides manufacturers with the testing infrastructure necessary to validate component reliability while accelerating time-to-market for critical automotive systems.

With the continued scaling of semiconductor packaging, ensuring reliable electrical contact in fine-pitch test environments has become a critical challenge. Conventional solutions such as pogo pins and wire-based probes reveal fundamental limitations when approaching the 0.2 mm pitch node, including constraints in spring miniaturization, reduced contact stability, and restrictions in manufacturing and assembly processes. In this work, we present a novel MEMS-based spring pin technology developed to overcome these barriers for 0.2 pitch package testing. By employing a differentiated high-aspect-ratio MEMS fabrication process, ultra-fine spring structures under 1 mm in length have been realized. The developed pins demonstrate current handling capability above 1 A, stable contact resistance below 0.2 Ω, low actuation force, and robust performance suitable for high-frequency and high-reliability evaluations. This poster will introduce the structural features and initial electrical/mechanical test results, and discuss the potential contributions of this technology to next-generation fine-pitch test applications.

반도체 패키징의 미세화가 지속됨에 따라, 파인 피치 테스트 환경에서 신뢰성 높은 전기적 접속을 구현하는 것은 중요한 과제로 부상하고 있다. 기존의 포고 핀(pogo pin) 및 와이어 기반 프로브는 0.2 mm 피치 노드에 접근할수록 스프링 구조의 최소화 한계, 접촉 안정성 저하, 제조 및 조립 공정상의 제약 등 근본적인 한계를 드러낸다. 본 발표에서는 이러한 장벽을 극복하기 위해 0.2피치 패키지 테스트용으로 개발된 새로운 MEMS 기반 스프링 핀 기술을 제안한다. 차별화된 High aspect ratui MEMS 공정을 적용하여, 길이 1 mm 이하의 초미세 스프링 구조를 구현하였다. 개발된 핀은 1 A 이상의 전류 구동 능력, 0.2 Ω 이하의 안정적인 접촉 저항, 낮은 작동 하중, 그리고 고주파·고신뢰성 평가에 적합한 우수한 성능을 보여주었다. 본 포스터에서는 구조적 특징과 초기 전기·기계적 평가 결과를 소개하고, 차세대 파인 피치 테스트 응용에서 본 기술이 가질 잠재적 기여를 논의하고자 한다.