March 9-12, 2014

Burn-in & Test Strategies WorkshopTM


BiTS is the world's premier workshop dedicated to providing a forum for the latest information about burn-in and test tooling, and related fields. At BiTS you'll find a comprehensive technical program, exhibits of the latest products and services, and many opportunities to meet, network and explore ideas with other test and burn-in strategies professionals.

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BiTS 2014


The paper(s) in this publication comprise the Proceedings of the 2014 BiTS Workshop. The content reflects the opinion of the authors and their respective companies. They are reproduced here as they were presented at the 2014 BiTS Workshop. This version of the papers may differ from the version that was distributed in hardcopy & softcopy form at the 2014 BiTS Workshop. The inclusion of the papers in this publication does n ot constitute an endorsement by BiTS Workshop, LLC or the workshop’ sponsors. There is NO copyright protection claimed on the presentation content by BiTS Workshop, LLC. (Occasionally a Tutorial and/or TechTalk may be copyrighted by the author). However, each presentation is the work of the authors and their respective companies: as such, it is strongly encouraged that any use reflect proper acknowledgement to the appropriate source. Any questions regarding the use of any materials presented should be directed to the author(s) or their companies. All photographs on this page are copyrighted by BiTS Workshop LLC. The BiTS logo and ‘Burn-in & Test Strategies Workshop are trademarks of BiTS Workshop LLC.  All rights reserved.

BiTS 2014 archive access requires registration.  To avoid yet another username and password, registration is through your LinkedIn account.  Register as a FREE guest, Full Conference Attendee (BiTS 2014), or a Subscriber. Traditional archive content is available to Guests; Premium content is available to Attendees and Subscribers. 
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Technical Program

BiTS Workshop 2014 offered a robust and riveting program featuring 35 papers presented during 7 podium and two poster sessions covering a host of test and burn-in related topics from a worldwide representation of authors.

Peter Ehlig, a Texas Instruments Fellow, taught this year’s Tutorial. In “Test 101: A Holistic View of Test”, Ehlig looked at test from the perspective of all its stakeholders, which includes not only Test Engineers, Test Equipment Suppliers, Quality Engineers, and Design For Test Engineers, but customers, end users manufacturers and more. Ehlig led a discussion on how test works or doesn’t work.

The Tutorial segued nicely into the TechTalk, led by Jeffrey L. Roehr of Texas Instruments. Roehr addressed “The Most Common Mistakes in Test” made by product and test engineers during test program development, characterization, and limit setting, and how to avoid them. He used examples of real products and real issues with how limits were set, or how data was interpreted, to highlight common and avoidable mistakes.

Keynote Speaker Last year’s Talking Points talk show introduced you to Interconnectology, a holistic approach to microelectronics manufacturing describing both technical interconnection, and supply chain partnership interconnection. This year’s Keynote Speaker, Simon McElrea, President at Invensas, the Interconnectology Company, explained why his company is spearheading this approach to manufacturing, and how it is more important than ever.

Distinguished Speaker.  Brandon Prior, Senior Consultant at Prismark Partners, returned once again to the BiTS Workshop with an overview of the global packaging market, focusing on emerging and fast growth package solutions. He have participants a glimpse of some cool product teardowns he used to illustrate his talk.

Invited Speaker.  Jan Vardaman, President & Founder of TechSearch International, discussed how wireless products are driving the unit volume growth in packaging today. In particular, the small size and weight of mobile devices are demanding very high volumes of wafer level packaging (WLP). Not only did she detail the trends for WLP in terms of pin count, die size, and pitch she also covered new packaging formats.

BiTS Feud.  Ever wonder how much the socketing guys really know about packaging trends? Attendees participated in a fun-filled hour where BiTS Honored Sponsors face-off in a heated contest, Family Feud-style, testing their knowledge and awareness. Based on a survey of the BiTS Workshop membership, the top 5 answers are on the board... Survey SAYS...!

Fred Taber of BiTS Workshop shared some socket market data with BiTS participants mined from recent Fleck Research research reports.  In addition, John West of VLSI Research discussed Market Forces Shaping the Socket Industry.

BiTS EXPO 2014
51 exhibitors, from socketing and related industries, exhibited their products and services during breaks in the technical program.  Click HERE for the exhibitor list of BiTS EXPO 2014.

BiTS 2014 brought together well over 300 participants, including nearly 250 full conference attendees, and 51 exhibitors from around the world, representing end users and suppliers of sockets, boards, burn-in systems, handlers, packages and other related equipment, materials and services.

BiTS 2014 in the Press

BiTS Workshop – The Next 15 Years by Ira Feldman - High Technology Business Development

BiTS Workshop – The Next 15 Years - Chip Scale Review magazine March/April 2014

BiTS 2014 Organizing Committee
Morton Jensen (Intel), Valts Treibergs (Multitest), Owen Prillaman (Tech-Connect Sales), Rafiq Hussain (Liberty Laboratories), Fred Taber (BiTS Workshop), Mike Noel (Freescale), Ira Feldman (Feldman Engineering),  Marc Moessinger (Advantest Europe), John Moore (Texas Instruments), Ila Pal (Ironwood Electronics)

Not pictured: John Hartstein (Sensata), Paul Boyce (Advantage Specialist)

BiTS 2014 Committee

BiTS 2014 Principal Sponsors
The BiTS Workshop would like to thank our principal sponsors for their continuing support of the workshop.
Premier Sponsor Honored Sponsors Distinguished Sponsors Publication Sponsor
R&D Altanova Twin Solutions

Sunday, March 9,  2014



Test 101: A Holistic View of Test

Peter Ehlig


Texas Instruments

View Presentation Audio, Video and Download PDF (Registration Required)

There are many stake holders with respect to the topic of test.  Peter Ehlig expected that the very audience represented Test Engineers, Test Equipment Suppliers, Quality Engineers, and Design For Test Engineers. All have areas of expertise and own perspectives.  Other perspectives  of interest to us include customer, the end user, the manufacturing sites, the boss and ther boss’ boss.

Peter's part of this seminar on Test 101, he discussed the fundamentals of test from the perspective of all stakeholders.  From a holistic view he lead a discussion on how test works, and his area of expertise, how test sometimes doesn’t work.

He lead a discussion as to take advantage of the expertise in the audience to work through some of the common challenges in testing today’s complex products. Having been involved in High Tech for over 3½ decades he has at least dabbled with most if not all these different perspectives and would opened the discussion to many challenges that might come across in areas such as: validation and characterization of test suites and hardware; Burn-in; power and temperature control; yield understanding; test cost; debug environments, etc.
Peter Ehlig has over 35 years of service in high tech industry, with experience ranging from high level system design and architecture to semi-conductor physics, and most of the places in between.

This broad range of experience provides a holistic view of quality, test, debug, and failure analysis. At the system level he’s worked with communications, computer, automotive, and military architectures.  At the device level he’s worked on CPU/DSP, embedded memories, and SOC architectures.  At the silicon level Mr. Ehlig has worked on optimization for performance, power, price, yield, and reliability.  When working on any new architecture, on any level, his approach is to maintain an appropriate balance across considerations of performance, power, price, manufacturability, testability, and rapid debug.

Mr. Ehlig is the Inventor/co-inventor on  44 US patents. He has published several papers and articles and has participated as a panelist on panel discussions at the International Test Conference and at the VLSI Test Symposium.



The Most Common Mistakes in Test

Jeffrey L. Roehr

Test and Data Analyst

Texas Instruments

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During the process of test program development, characterization, and limit setting, there are some common mistakes that can be made by Product and Test engineers. Issues like ‘data that is too good to be true’, not understanding the limitations of using a Standard Deviation, passing devices with “0” values, and limits that allow for the ‘physically impossible’ such as negative supply currents. Examples of real products and real issues (including those with test tooling), with how limits were set, or how data was interpreted, are used to highlight some of the most common (and 100% avoidable) mistakes.

Jeffrey Roehr has over 30 years of experience in Product and Test Engineering and Management for RCA, GTE, Analog Devices, Mediatek, and is now working for Texas Instruments (MCU/C2000) in Houston.

For the past 10 years his focus has been on developing algorithms for adaptive testing, outlier elimination, and statistical testing on very high volume production products.

Mr. Roehr has presented many papers, tutorials, and invited talks at IEEE events. He is a Senior Member of the IEEE, the Technical Program Chair of the IEEE DATA workshop, a member of the ITRS Adaptive Test working group, and is the founder and chairman of the Texas Instruments Data Analysis Workshop (DAW).


Distinguished Speaker

Packaging And Interconnect Trends: QFN, WLCSP, Fine Pitch And Modular/3D Solutions

Brandon Prior

Senior Consultant
Prismark Partners

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Mr. Prior shared an overview of the global packaging market, with a focus on emerging and fast growth package solutions.  In his presentation he reviewrd where package miniaturization and modularization has taken us so far, and where it will lead in the next 5 years. Teardowns of high density boards and packages are used to illustrate key points.
Mr. Prior is a Senior Consultant at Prismark Partners.  He joined Prismark in 1996 and is the author of their Semiconductor and Packaging Report. In his role at Prismark, he provides market and competitive analyses within semiconductor packaging and interconnects.

The Latest Information on Important Topics in Burn-in & Test of Packaged ICs will be Presented
at 7 Podium Sessions and Two Poster Sessions

Monday, March 10, 2014


Opening Remarks

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Welcoming remarks from the General Chair, Fred Taber

BiTS 2014 Keynote Address

Interconnectology - The Road to 3D

Simon McElrea

Invensas Corporation

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Interconnectology is everything involved with getting “Silicon into Systems”: a holistic approach describing both technical interconnection and supply chain partnership interconnection. Nowhere does this concept apply more than in the commercialization of 2.5D and 3D integration technologies. From design, to processes, and equipment and material development, to manufacturing and test, 2.5D interposer products and 3D ICs require collaboration across the value chain to achieve high yielding devices, optimum cost-of-ownership and rapid time-to-market: all critical elements for today’s consumer-driven market. Further, the middle-end-of-line (MEOL) processes require engineering knowledge that spans front- and back-end processing through to packaging, assembly and test. Consumer trends that are bringing about the need for Interconnectology to be adopted as a concept industry wide will be discussed.

Mr. Simon McElrea is President of Invensas Corporation, a wholly owned subsidiary of Tessera Technologies Inc., and a global leader in semiconductor technology and intellectual property. Prior to founding Invensas in April 2011, he led marketing, business development and worldwide engineering functions at Tessera.

He was Interim CEO of Vertical Circuits Inc. until 2010, and has been a managing partner of Alpha Venture Consulting since 2006. Prior to this, he held leadership roles in operations, engineering, and business unit management at Amkor Technology, Honeywell Electronic Materials, and Johnson Matthey PLC. A native of Northern Ireland, Mr. McElrea has worked in Asia, North America and Europe, specializing in startup ventures and corporate turnarounds.

He holds Bachelor’s and Master’s degrees, with honors, in Engineering and Management from Oxford University.


Session 1

 A Clean Start
There's no doubt about it, clean contacts in contactors and sockets work a lot better than dirty ones. So what better place to start looking at burn-in and test strategies than with a close look at contamination control and cleaning processes to improve yields, test time and re-test reduction? This session begins with three hypotheses of the causes for contact contamination, Along with guidance on procedural changes for improved performance. The next presentation offers a solution to the havoc high temperature burn-in can wreak on devices under test (DUTs) with a specialized coating process to prevent solder contamination of contacts and deformation of the solder bumps on the DUT. The final two presentations examine online cleaning processes. The first focuses on a characterization tool that determines the effectiveness of online cleaning, while the second is directed at an automatic cleaning solution for a bowl fed handler used with a RF contactor. Hey, it's a dirty job, but somebody's got to do it.
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"Contamination Mechanisms of Contact Probes"

Jon Diller
Smiths Connectors | IDI

Kevin DeFord
Smiths Connectors | IDI


"Special Coating Cleans-Up a Mess"

Paul Ruo
Aries Electronics, Inc.

Erik Orwoll
Contact Coatings, LLC

"Unique Methodologies for Investigating On-line Cleaning Process Parameters and Recipe Optimization"

Jerry Broz, Ph.D.
International Test Solutions, Inc.

Soheil Khavandi
International Test Solutions, Inc.

Bret Humphrey
International Test Solutions, Inc.

"Yield and Test Time Improvement via Automated Online Cleaning"
Most Inspirational

Brent Edington



BiTS Feud Socket Company Face-off
Co-sponsored by:
impress labs
Françoise von Trapp Queen of 3D
Founder of 3D InCites
Interconnect Devices, Inc.
Captain: Gabriel Guglielmi

Sensata Technologies
Captain: David Barnum

View Presentation Audio, Video and Download PDF COMING SOON!

How about this for an unusual event at a workshop? Last year BiTS hosted a talk show, this year a game show!

This was the BiTS Workshop’s version of Family Feud. Two leading socket companies faced-off in a heated contest of ‘BiTS Feud’. This fun-filled and informative hour, each team was quizzed on which company knows more about the latest packaging trends, as determined by a survey of their peers!

Answers were based on a survey taken of the BiTS Workshop’s membership, the top answers are on the board... Survey SAYS...!

BiTS will made a donation to the winning team’s charity of choice.

Françoise von Trapp blogs about emerging 3D integration technologies on the online community she established, 3D InCites. Previously Sr. Technology Editor at Chip Scale Review and Managing Editor of Advanced Packaging Magazine, she now hangs her hat at Impress Labs, where she serves as subject matter expert for the agency’s clients in the semiconductor space.

Gabriel Guglielmi is VP, Business Development & Strategy at Interconnect Devices, Inc. (IDI).
Interconnect Devices, Inc. is a leading provider of spring probes, test sockets & interfaces. IDI’s sockets support most package configurations, provide high cycle life, consistent resistance, bandwidths >30 GHz & I/O pitches less than 0.25 mm.

David Barnum is Senior Director, Global Business Unit Manager at Sensata Technologies.
Sensata Technologies is the world’s largest supplier of sensors and electrical protection across a broad range of markets and applications. The Qinex business Unit is a leading supplier of thermal solutions and burn-in sockets for Memory & Logic Applications, for IC Packages from 1.27 mm - 0.3 mm pitch.


Poster Session 1


Download PDF(Registration Required)

If one was good, two must be better! Poster Sessions that is! We had so many qualified submissions this year, we divided them in to two Poster sessions offering a variety of relevant topics to augment what you'll learn sitting in the Podium sessions.

Poster Sessions are a great way to network through interaction with the poster presenters and other curious bystanders, multitask during a break and stretch your legs after a long session.

"One-Piece Stamped and Formed Probe Pin"

Ichiro Fujishiro
Yamaichi Electronics

"Correlation and Measuring Techniques for +/-5% Impedance"

Tom Bresnan
R&D Altanova

"Compliance Grounding - The Mechanical Importance of Grounding"

Shamal Mundiyath
JF Microtechnology Sdn Bhd


Session 2

 Doing the Heavy Lifting

Within burn-in and test strategies the heavy lifting that falls to the technologies within test systems is this session's focus. The first paper outlines the issues related to Kelvin contacting for wafer-scale test and presents a solution to these obstacles. The second paper discusses a temperature study of high power switching regulators with thermal shutdown to develop an accurate method of determining junction temperature rise. The final paper introduces using MEMS in place of traditional electro-mechanical technologies.
View Presentation Audio, Video and Download PDF (Registration Required)
"Kelvin Contactors for Wafer-Level Test"
Jim Brandes
Multitest - LTXC
"Temperature Characterization of High Power Switching Regulators"
Paolo F. Rodriguez
Analog Devices
"LIGA Precision Microfabrication for Electromechanical Applications"
Attendee Choice

Frank Schonig
Innovative Micro Design


Tuesday, March 11,  2014


Session 3

 Show Them What We're Made Of
Microelectronics continually tests the limits and ingenuity of test and burn-in strategies. So, more and more, the onus falls on materials solutions for sockets. This session kicks off with an examination of available socket materials to foster a better understanding of their relative merits for various applications, plus there's a sneak preview of coming material trends. The continuing trend of tighter pitches, higher temperatures and higher density contacts places heavy demands on test probes and equipment, particularly the materials used to manufacture them. As these materials continuously evolve, finite element modeling can help designers demonstrate the effects of material properties and performance as you'll learn in the second paper. The third presentation focuses on high temperature burn-in for automotive applications, emphasizing advancements in contact pin plating and surface finishing technologies to address the thermal challenges being faced. Wrapping up this session is a case study comparing three types of palladium alloys for spring pin contactors to determine what the best material is for test.
View Presentation Audio, Video and Download PDF (Registration Required)
"The Stuff We’re Made Of
An Examination of the State of the Art in Socket Materials"
Best Data

Jon Diller
Smiths Connectors | IDI

"Rising to the Challenge:  Material Evolution to Enable Reliable Performance at Tighter Pitches and Higher Temperature"
Best Tutorial

Mike Gedeon

"180 Deg. C BGA Burn-in, Is It Doable?"

Kenji Ichihara
Yamaichi Electronics Co., Ltd.

Masaru Sato
Yamaichi Electronics Co., Ltd.

Noriyuki Matsuoka
Yamaichi Electronics Co., Ltd.

Jec Sangalang
Yamaichi Electronics USA

"Palladium Alloy Hardening and Wear Away Characteristics"

Takuto Yoshida
Test Tooling Solutions Group

Craig Hudson
Test Tooling Solutions Group


Poster Session 2


Download PDF(Registration Required)

If one was good, two must be better! Poster Sessions that is! We had so many qualified submissions this year, we divided them in to two Poster sessions offering a variety of relevant topics to augment what you'll learn sitting in the Podium sessions.

Poster Sessions are a great way to network through interaction with the poster presenters and other curious bystanders, multitask during a break and stretch your legs after a long session.

"In-Situ Debug Techniques of SATA Connectors in Storage Servers - and Connector Degradation Phenomena"

Trent Johnson
Cleversafe, Inc.

"Investigation of Micro Spring Performance"
Best Poster

Jiachun (Frank) Zhou
Smiths Connectors - IDI

Hui Liu
Smiths Connectors - IDI

"Testing Elastomer for HTOL"

Ila Pal
Ironwood Electronics, Inc.

Meghann Fedde
Ironwood Electronics, Inc.

Sultan Faiz
Ironwood Electronics, Inc.

Ranjit Patil
Ironwood Electronics, Inc.


Session 4

 The Market is Open
The BiTS Workshop just wouldn't be the BiTS Workshop without at least one presentation on the test and burn-in marketplace.  In this year's three presentations, first we'll hear about the technical and market forces that are shaping the future of test and burn-in, particularly the challenges of industry cycles with the never ending quest for reduced costs. Next up will be our own Fred Taber, with his fourth annual Socket Report on the size of the market, whether its shrinking or growing, and companies that are leading the charge. This session's final paper hones in on a market technology trend with one innovative high-density package-on-package (PoP) solution requiring test hardware to accommodate fine pitch wire-tip interconnects. Socket and test hardware development and verification studies are underway to take this technology to high volume manufacturing.
View Presentation Audio, Video and Download PDF (Registration Required)
"The Technical and Market Forces Shaping the Future of Test and Burn-In Sockets"

John West
VLSI Research, Inc.

"Socket Marketplace Report"

Fred Taber
Taber Consulting

"Manufacturing Readiness of Bond Via Array (BVA™) Technology for Fine-Pitch Package-on-Package (PoP)"

Rajesh Katkar

Rey Co

Wael Zohni


Session 5

 Sockets With Integrity
High frequency signal and power integrity with sockets are essential to successful package testing. The opening presenter shares first-hand experience pairing the design of a high-speed load board with sockets of the desired bandwidth to avoid significantly reduced system performance. The second paper assesses power and ground performance through an examination of signal and power routings and the corresponding ground return paths for a PCB/socket combination. The final presenter looks at how ever shrinking devices with more functionality and higher density I/Os bring sensitive signal lines closer together, contributing to signal integrity issues.
View Presentation Audio, Video and Download PDF (Registration Required)
"High Bandwidth Sockets For SERDES Applications On ATE Load Boards"
Best Paper/Presentation

Don Thompson
R&D Altanova

"Signal and Power Integrity Impact of Ground Slugs in Sockets"

Gert Hohenwarter
GateWave Northern, Inc.

"Building Blocks and Predictors for Good Contactor Signal Integrity"

Jeff Sherry
Johnstech International

Wednesday, March 12,  2014


Session 6

 Interconnectology: It's What We Do
Last Year's BiTS workshop introduced the benefits from the Interconnectology approach of collaboration across the supply chain from device design to test. This session focuses on interconnect designs and advancements. As contactor design has had to evolve to address shrinking pads and decreasing pitches, there's lower contact force. The first presentation details the development of long-life stamped spring probes in response to challenging technology roadmaps, all at a cost that includes maintenance and replacement costs. Next up is a paper on validations sockets (used for post-silicon validation and are quite different from test sockets). This paper brings awareness to these sockets and their challenges to encourage industry collaboration for solving future post-silicon validation interconnect challenges. The session concludes with an exploration of crosstalk sources and discusses solutions and emerging technologies, including costs, to reduce crosstalk. See? It's all about Interconnectology.
View Presentation Audio, Video and Download PDF (Registration Required)
"Long Life / Stamped Spring Probe Development"

Samuel Pak
IWIN Co. Ltd.

A.J. Park
IWIN Co. Ltd.

"Validation Interconnect Socket - Application and Future Challenges"

Ashok Kabadi
Intel Corporation

"Crosstalk Mitigation in ATE Socket-Device Interface Boards"

Thomas P. Warwick
R&D Altanova, Inc.



Session 7

 Feel the Burn-in
Burn-in is used to ensure a device's reliability and lifetime. The two papers in this final session look at parallel burn-in methods. The first presents an overview of built-in IC test and monitoring methods and describes the access buses for these test and monitor methodologies. It will also describe a hardware and software framework that exploits these test technologies for the massively parallel burn-in and test of 100's of complex ICs. The second presents some interesting challenges along the road to parallel burn-in test. It will include design requirements and rules to optimize the overall device power consumption; and go one step further on managing the unexpected challenges.
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"Massively Parallel Burn-in Test using IC Serial Buses"

Billy Fenton
OLAS Consulting

Pat Mitchell

"Challenges of Increasing Parallelism in Burn-in Testing"

Yeow Hock Low
Infineon Technologies Asia Pacific


Invited Speaker

 Trends in Wafer Level Packaging: Thin is In!

E. Jan Vardaman

President & Founder
TechSearch International, Inc.

View Presentation Audio, Video and Download PDF (Registration Required)
Wireless products continue to drive the unit volume growth in semiconductor packaging today. Growth in wafer level packages (WLPs) continues to be driven by the strong preference for small form factor, low profile packages for use in mobile phones. WLPs with a variety of pin counts and die sizes are also found in watches, MP3 players, digital cameras, laptops and tablets. Pin counts are increasing and ball pitch is decreasing. New WLP formats are emerging. Fan-out WLPs (FO-WLPs) are receiving increased interest for more than just single die package and are emerging as a new potential format for SiP. This presentation examines application trends for WLPs, trends in pin count, die size, and ball pitch, as well as new package formats.
Mrs. E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided licensing and consulting services in semiconductor packaging since 1987. She is the co-author of How to Make IC Packages (published in Japanese by Nikkan Kogyo Shinbunsha), a columnist with Circuits Assembly/Printed Circuit Board Fabrication, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She is a member of IEEE CPMT, SMTA, MEPTEC, IPC, IMAPS and SEMI. She was elected to two terms on the IEEE CPMT Board of Governors. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium. She has made numerous presentations on developments in advanced packaging.
Awards / Closing Remarks View Presentation Audio, Video and Download PDF

It was three days packed with learning, exploring and sharing. Fred Taber shared a few closing remarks and some recognition to the people and papers that have distinguished themselves in one way or another at BiTS 2014.


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