Welcome to the TestConX Virtual Event!
Registered participants in the 2020 Virtual Event have access to the slides and videos for the presentations and posters from this page.
You need to register to participate in the virtual event
If you are registered please login to access this content. Otherwise please register here.
Be sure to reserve time for the live interactive presentations on May 11-13, 2020. The default schedule is for the sessions are 7 - 10 am and 5 - 7 pm Pacific time for each day. Once the schedule is confirmed you will be notified.
Most importantly, please stay safe and healthy during this challenging time!
Ashok Kabadi, Ila Pal, & Ira Feldman
on behalf of the entire TestConX organization
Designers and test engineers working on 5G and millimeter-wave (mm-wave) devices require accurate, fast, and cost-effective test solutions. Not only are 5G waveforms wider and more complex, there are many new high-frequency challenges including the need to perform over the air (OTA) testing. Presentations cover the need for a low-cost socket using a single measurement near field antenna, strategies to support upgrading from current automated test equipment (ATE) operating at < 6 GHz testing to mm-wave frequencies, and signal transmission with minimal loss using specially designed impedance matched printed circuit boards (PCBs). In addition, the higher bandwidth and data rates have driven the development of advanced modulation schemes such as 400G Ethernet phase amplitude modulation using four levels (PAM4) signaling to support high speed applications such as silicon photonics. New test strategies are required to cost effectively test all of these emerging application as described.
Fifth generation (5G) applications are utilizing millimeter wave bands to increase mobile device radio bandwidth. And to reduce the overall size of these devices, antenna in package (AIP) technology is being adopted to meet market requirements. AIP poses a significant test challenge since these transceiver devices must be accurately signal tested “over the air” (OTA) in near and far field regions with the antenna possibly located on the top, bottom, or sides of the semiconductor package. Not only does the signal power and uniformity need to be measured but the ability to ‘beam steer’ needs to be characterized. These four presentations address the challenges of testing AIP devices OTA.
Over the Air (OTA) Antenna TestingApril 7, 2020
5G mmWave AiP validation test: Achieving lower measurement uncertainty and higher speedsApril 7, 2020
Over the Air Test Solution for New 5G / mm-Wave Band Wireless ICsApril 6, 2020
Spring Probe Pins Enabling Extremely High Speed -1db @ 80 GHzApril 6, 2020
Printed Circuit Boards (PCBs) which are the basic electrical and mechanical infrastructure of many test solutions are continually pushed to the limits by semiconductor test applications. We will start with a review of the state of the art in fine pitch load boards and the associated manufacturing challenges. Then an explanation of how Artificial Intelligence (AI) / machine learning-based smart router solution was implemented to significantly improve microprocessor PCB interposer layout will be discussed. Lastly, the simulation, measurement, and optimization of power integrity (PI) issues typically found on high speed and high channel count networking chips will be examined.
It is essential that interface hardware is properly validated before deploying in high volume manufacturing (HVM). As test complexity and requirements have increased, so has the need to properly complete the validation using handling equipment ideally in a lab environment. A new methodology introduced allows many environment variables to be tested simultaneously including temperature and current during cycle testing. The method presented leads to shorter lead-times, quicker ramps, less downtime, and reduced time to market. Radio frequency complementary metal oxide semiconductors (RFCMOS) system-on-chip (SoC) devices primarily used in automotive radar for advanced driver-assistance systems (ADAS) applications require specialized test cells. The integration of test cells with the right automated test equipment (ATE), innovative contact technology, and tri-temperature capable part handlers to support 81 GHz socketed test solutions will be described. Lastly, a wafer probe test cell utilizing built-in self-test (BiST) for second generation 80 GHz radar transceiver modules with high level integration of transmit, receive, and voltage-controlled oscillator (TX, RX, & VCO) functions in one device will be presented.
This session provides a deeper understanding of test hardware, especially sockets, electrical signal integrity (SI) requirements of crosstalk, impedance, eye height, etc. The printed circuit board (PCB) itself has the potential to become a major crosstalk contributor in the socket-to-IC interface area. A SI analysis of the socket combined with the PCB interface will demonstrate the need for comprehensive analysis if meaningful results are desired. Next the signal integrity issues of co-axial spring-pin sockets for high-speed device test will be compared to solutions using rubber sockets with impedance matching. As high-speed data rates increase rapidly for bus protocols like PCIE4.0, higher levels of electrical isolation are required in all aspects of the test hardware especially the socket. The last presentation compares the isolation and signal quality provided by different socket types including coaxial and non-matched configurations.
Advances in semiconductor manufacturing creates significant challenges in validating silicon designs and performance. A creative solution using modular multi-domain power delivery platform for sub-7 nm system-on-chip (SOC) silicon validation is presented. And there are new tester requirements for harsh radiation environment testing for soft error rate measurement. The process of qualifying and releasing a new package level tester for proton high energy beam testing is described. Next, at the system-level there many challenges in bench testing and validation of silicon due to complexity in system board integration. A breakthrough solution to this problem will be presented that simulates the physical oscilloscope function with a field programmable gate array (FPGA) to improve the overall test time. Finally, while 3D packaging provides high performance it introduces thermal and mechanical challenges due to the package complexity. A novel split-socket concept is shown that bypasses the memory and provides a conductive path directly to the 3D package.
Design of Modular Ultra-Low Voltage Power Delivery System for Sub-7nm SOC ValidationApril 7, 2020
New Tester Qualification using Parallel Test & Correlation for Soft Error Rate MeasurementsApril 7, 2020
99% Validation Efficiency Through Cloud Power SequencingApril 7, 2020
Thermal Challenges in Enabling Validation & Test of 3D Package on PackageApril 7, 2020
There are thermal test challenges at both wafer-level and system-level. Wafer-level High-Temperature-Operating-Life-Test (HTOL) case studies and solutions will be shown as the fastest way to identify early reliability failure mechanisms. Next, the key challenges and a solution for the biased-life stress testing of high-power IC products will be offered. As integrated circuit (IC) power densities increase, traditional cooling approaches using heatsinks are reaching their limits. The advantages and disadvantages of other available cooling solutions including heat-pipes, cold plate with chiller, thermoelectric cooling, and thermal bath will be discussed for different power requirements. In the final presentation, the thermal challenges of automotive device reliability testing and time-to-market is covered. A system level test (SLT) solution with individual active thermal control (ATC) for reliability testing at extreme temperatures across 480 sites will be discussed.
With data rates continuing to climb and package pitch continuing to scale down, it is increasingly difficult to provide cost-effective package test interconnect solutions that meets stringent mechanical and electrical requirements. First a high-speed contact design to support high data rates is shown to meet cycle life, force-resistance, and signal integrity (SI) requirements. Then an advanced hybrid coaxial high-performance socket fabricated by 3D micro-electro-mechanical system (MEMS) process is described. The presentation will show electrical characterizations using both 3D-electromagnetic simulation and evaluation results. Lastly, the issues of cleaning the pads of the printed circuit board (PCB) and device when using traditional spring-pins is discussed. A test socket using MEMS particles on rubber will be shown to have less tin migration resulting in lower damage to the PCB and device pads.