Shanghai November 13, 2025
Workshop registration includes all technical sessions, the TestConX EXPO, buffet lunch, morning & afternoon tea breaks, and download of the Proceedings.
TestConX, over the course of its twenty-six-year history, has established itself as the preeminent event for test consumables, test cell integration, and test operations. The program scope includes packaged semiconductor “final” test, burn-in, system level test, and beyond to encompass all practical aspects of electronics testing such as validation, advanced packaging testing, module test, and finished product test.
Join us in-person for the 11th annual TextConX China! You will not want to miss this opportunity to be part of TestConX as we connect a larger community of test professionals and to participate in this excellent event!
Thursday November 13, 2024
9:00
“CoWoS与CoPoS先进异构集成封装中AI-HPC的测试插入点与测试挑战”
Abstract (English)
Abstract
As AI-HPC (High Performance Computing) solutions continue to evolve from single compute devices (GPUs or Switches) into advanced heterogeneous integrated packages with multiple chiplets (e.g., HBMs, GPUs and Switches with UCIe interfaces, Silicon Photonics ICs, etc.) in a silicon wafer or panel interposer (aka CoW: chip-on-wafer; CoP: chip-on-panel), and then on to the final package substrate (CoWoS: chip-on-wafer-on-substrate), the test complexity is increasing significantly, as well as the number of possible test insertions.
This presentation provides an overview of this trend and related new test challenges which also require new test strategies that will guarantee both known-good-die and known-good-CoW to optimize the overall cost of test, while maximizing the final test insertion yield and quality of the finished CoWoS device.
摘要 (Chinese)
随着AI-HPC（高性能计算）解决方案持续演进，从单一计算器件（如GPU或交换机）发展为采用硅中介层或面板中介层（即CoW：晶圆上芯片；CoP：面板上芯片）的、集成多芯粒（例如HBM、带UCIe接口的GPU和交换机、硅光芯片等）的先进异构集成封装，并最终搭载于封装基板之上（CoWoS：基板上晶圆上芯片），测试的复杂性以及潜在的测试插入点数量均显著增加。
本演讲将概述这一趋势及相关的新测试挑战，这些挑战也要求新的测试策略，以保证已知良品芯片和已知良品CoW，从而优化总体测试成本，同时最大化最终CoWoS器件的测试直通良率与产品质量。
“驾驭市场变局：AI时代测试与老化插座的未来”
Abstract - Biography (English)
The explosive growth of artificial intelligence is creating new challenges and market imbalances within the semiconductor industry. At the same time, governments are intervening through subsidies, tariffs, and other protectionist policies. The result of these powerful drivers will be a redefinition of global competition across the supply chain.
This presentation examines how these forces are driving today’s market transformation and their implications for suppliers and buyers of test and burn-in sockets, highlighting both the risks and opportunities that lie ahead.
John West is a Senior Director of the Semiconductor Subsystems and Test Division at Yole Group. He has over 20 years of industry experience and a successful track record in various strategy and consulting projects.
John has a Bachelor's degree in Medical Physics from King's College London and an MBA from Cranfield School of Management.
摘要 (Chinese)
人工智能的爆炸性增长正在半导体行业内引发新的挑战与市场失衡。与此同时，各国政府正通过补贴、关税及其他保护主义政策进行干预。 这几股强大驱动力的共同作用，将重新定义贯穿整个供应链的全球竞争格局。
本演讲将审视这些力量如何驱动当前的市场变革，并分析其对测试与老化插座的供应商及采购商所产生的影响，重点揭示未来所蕴含的风险与机遇。
10:45
Break & Networking
Enjoy time to meet with the presenters and network while refreshments are served.11:15
“摘要标题: 汽车电子芯片上不同类型收发器在爱德万测试V93000平台上的测试方案”
Abstract - Biography (English)
Automotive System Basis Chip (SBC) is an integrated component that combines common system features required on automotive ECUs, such as communication transceivers, voltage regulators, diagnostics and supervision functions, switches, and wake inputs. As a crucial communication transceiver, CAN transceiver is applied into engine control, transmission, and braking successfully. Under the situation of digitization, electrification, and automation in the flied of automotive, traditional CAN transceiver (1Mbit/s, 8Bytes Payload) is hard to meet all kind of application requirements. The newly developed CAN-FD signal improvement capability (8Mbit/s, 64Bytes Payload) by BOSCH is more prevalent in sophisticated ADAS and AV applications and lead the industry, which also bring test challenges into ATE inevitably.
First, the CAN-FD test principle is introduced in this paper. For CAN-FD, mainly the timing test, that is propagation delay includes TXDCAN to CANH/L DIFF (ns), TXDCAN to RXDCAN (ns) and CANH/L DIFF to RXCAN (ns), which are all very demanding with the nano-seconds level resolution and sensitive to CAN-FD differential load circuit. In additional, the complicated algorithm for differential signal is the last but not the least part to guarantee the test specification.
Second, this paper will illustrate the CAN-FD differential CANH/CANL load circuit design. On the one hand, PS1600 and AVI64 differential pair must be for CANH and CAHL. CANH should be positive in differential pair. For example, CH1/CH3, CH2/CH4 for AVI64 and A1/A3, A2/A4 for PS1600. Same trace length should be over all sites for site correlation which we have seen from case study in evaluation board. On the other hand, the load circuit between CANH and CANL selects symmetrical resistors combination by mechanical relay G6K for different load condition.
Based on above, this paper provides almost all possible test solutions according to some real SBC projects. These solutions mainly focus on CANH/CANL as below:
- Solution A: Error map with single end PS1600 400Mbps license receive edge x8 mode.
- Solution B: Digital capture with single end PS1600 base license 100Mbps and receive edge x8 mode.
- Solution C: High speed digital capture with single end PS1600 base license 100Mbps and receive edge x8 mode.
- Solution D: TMU with PS1600 DIFF COMP.
- Solution E: Step up single end PS1600 digital capture edge by loop inside one test cycle to achieve high granularity in the condition of limited license.
Solution A to D all can be a solution for production all the time. The solution E is an old solution due to limit digital speed of 50Mbps. At current phase, digital instrument base license is much faster and will obsolete the solution. Nevertheless, the theory is very constructive for future in case of digital speed is limited and could not reach the resolution on request of more challengeable test specification.
Finally, this paper will analyze the correlation at certain CAN rate and test results when CAN Flexible Date Rate is 2M and 5M individually. This paper also concluded that 60 Ohm resistor load between CANH and CANL has got higher signal quality than what it is at 50 Ohm and 65 Ohm resistor load in the real case study.
Biography
Jibao Fan
Expert Engineer
Jibao Fan, from ADVANTEST China, is an expert engineer. He joined Advantest China in 2018. His work scope includes test solution design for automotive, mobile phone and AI/HPC chips, test program development, and consulting with top semiconductor companies for a long time.
摘要 - 简介 (Chinese)
汽车系统基础芯片（SBC）是一种集成组件，它将汽车电子控制单元（ECU）所需的常见系统功能整合在一起，例如通信收发器、电压调节器、诊断和监控功能、开关以及唤醒输入。作为关键的通信收发器，CAN 收发器已成功应用于发动机控制、变速器和制动系统。在汽车领域数字化、电气化和自动化的背景下，传统的 CAN 收发器（1Mbit/s，8 字节有效载荷）难以满足各种应用需求。博世新开发的 CAN-FD 信号改进能力（8Mbit/s，64 字节有效载荷）在复杂的高级驾驶辅助系统（ADAS）和自动驾驶（AV）应用中更为普遍，并引领了行业的发展，这也不可避免地给自动测试设备（ATE）带来了测试挑战。
本文首先介绍了 CAN-FD 的测试原理及差分 CANH/CANL 负载电路的设计，并基于实际 SBC 项目提供了多种测试解决方案，具体如下：
- 解决方案 A：使用单端 PS1600 400Mbps license接收沿 x8 模式的 Error map。
- 解决方案 B：使用单端 PS1600 基本 license 100Mbps 和接收沿 x8 模式的 digital capture。
- 解决方案 C：使用单端 PS1600 基本 license 100Mbps 和接收沿 x8 模式的高速 digital capture。
- 解决方案 D：使用 PS1600 DIFF COMP 的 TMU。
- 解决方案 E：在单个测试周期内通过循环提升单端 PS1600 数字采集边缘，以在 license 有限的情况下实现高精度。
解决方案 A 至 D 始终可用于生产。解决方案 E 是旧方案，因为其数字速度限制在 50Mbps。目前阶段，数字板卡基础 license 的速度要快得多，该方案将被淘汰。不过，该理论对于未来数字速度受限且无法达到更具挑战性测试规范要求的分辨率的情况仍具有建设性意义。最后，本文分析了不同 CAN 速率与测试结果之间的相关性，并得出结论：在实际案例研究中，CANH 和 CANL 之间 60 欧姆电阻负载的信号质量优于 50 欧姆和 65 欧姆电阻负载。
个人简介
樊吉宝
专家工程师
樊吉宝，隶属于爱德万测试（中国）管理有限公司，专家工程师。2018 年加入爱德万测试中国，主要负责汽车电子芯片、手机芯片和 AI/HPC 芯片测试方案的设计、测试程序的开发以及相关的咨询工作，长期与行业顶尖的半导体公司进行项目的开发以及管理工作。
“在RMA调查中实施有效测试限值以实现快速根因分析”
Abstract - Biography (English)
Return Material Authorization (RMA) investigations are essential for semiconductor quality assurance, enabling functional failures to be traced back to their root causes. In this study, we examine an RMA case in which a production device exhibited a complete loss of critical timing measurements after an unspecified period in service. Automated Test Equipment (ATE) and bench tests revealed that one channel failed to meet multiple timing specifications, while the other channel remained within acceptable limits which highlighted a clear functional divergence.
To isolate the anomaly, register-level readback tests were added to the test program. These tests consistently showed deviations in specific comparator configuration registers on the failing channel, confirming a localized functional fault. Guided by these electrical test results, a structured failure analysis protocol was initiated. The device was decapsulated and subjected to high-magnification optical inspection, which identified a process-related defect: metal-to-metal shorting across parallel interconnect lines within the comparator block.
Focused Ion Beam (FIB) cross-sectioning and Scanning Electron Microscopy (SEM) further characterized the defect, revealing a foreign particle lodged beneath the passivation layer at an interconnect level. Energy Dispersive X-ray Spectroscopy (EDS) analysis determined the particle composition to be tungsten, thereby confirming its role in creating an unintended conductive path that led to register read/write failures.
This case study underscores the importance of defining precise test limits and incorporating comprehensive functional coverage. Tests that span both channel-level performance metrics and register-level checks can help efficiently formulate and validate root-cause hypotheses. By establishing dynamic specification boundaries and augmenting ATE programs with targeted register tests, latent fabrication defects can be detected early, streamlining physical failure analysis (PFA) efforts.
Implementing this integrated approach not only reduces RMA turnaround time and associated costs but also feeds back into production test development, enhancing screening effectiveness to prevent future escapes. We conclude with recommendations for optimizing test programs such as adaptive limit setting, expanded register functional coverage, and closer collaboration between test engineering and failure analysis teams to bolster overall product reliability and accelerate root-cause resolution in high-volume semiconductor manufacturing and production.
摘要 - 简介 (Chinese)
退货授权（RMA）调查是半导体质量保证的关键环节，能够将潜在的功能失效追溯至其根本原因。在本研究中，我们分析了一起RMA案例：量产器件在服役一段时间后，其精密测量模块的精度指标出现退化。自动测试设备（ATE）与台架表征揭示了明显的通道差异：失效通道无法保持所需的精度规范，而其他通道则仍在规格范围内。
为了隔离并验证失效机理，进行了有针对性的电应力测试，并结合早期失效率（ELFR）验证实验。这些实验不仅验证了新的ATE筛选方法的有效性，还在后续RMA中得到进一步确认，证明其在识别潜在器件缺陷方面的价值。局部电异常测试为后续失效分析提供了方向。通过去封装、高倍光学显微镜检查以及扫描电子显微镜（SEM）分析，确认了受影响电路中存在与工艺相关的缺陷，并与观测到的电气失效形成了物理对应。
本案例强调了精确定义测试限值的重要性，并指出通过结合基于应力的验证方法来增强ATE测试覆盖度，可以更有效地检测潜在的制造缺陷。利用动态规范边界与ELFR验证的筛选机制，测试工程团队能够加速根因定位并缩短RMA处理周期。这一综合方法不仅减少了客户影响和相关成本，同时也提升了量产筛选的有效性。我们最后提出优化测试方案的建议，包括自适应限值设定、基于应力的覆盖扩展，以及产品工程与失效分析团队的紧密协作，以增强高产量半导体制造中的长期可靠性。
12:15
Lunch and EXPO
Enjoy the delicious hot buffet lunch and networking time. Then take the time to explore the TestConX EXPO. There will be many great exhibits to connect electronic test professionals to solutions. You will be certain to see something new or meet someone new. As attendees to TestConX know, there is always excellent food, drinks, and time for attendees to network with exhibitors! TestConX EXPO will open at 12:15 and will remain open throughout the afternoon until 18:0013:15
“人工智能无所不在时代的测试挑战与方向”
Abstract (English)
The exponential growth of AI-related applications in the past decade has been nothing short of astounding. This growth is both enabled by and driving advances in semiconductor scaling and heterogeneous integration technology. With the proliferation and complexity touching all aspects of our lives, concerns about reliability and safety naturally arise. Testing lies at the core of reliability assurance, which begs the question: Are current test methods and practices keeping up? In this talk, I will explore this question in more depth in terms of challenges and shortcomings, solutions needed, and the key role AI will play to help test technology keep up the pace.
摘要 (Chinese)
在过去十年中，与人工智能相关应用的指数型成长令人惊叹。这种成长既得益于半导体技术的持续微缩与异质整合技术的进步，同时也推动了这些技术的发展。随着人工智能的普及与复杂性渗透到我们生活的各个层面，对于可靠性与安全性的疑虑也随之而来。测试是确保可靠性的核心，因此我们不得不问：现有的测试方法与实践是否跟得上时代的脚步？在这场演讲中，我将从挑战与不足、所需的解决方案，以及人工智能在协助测试技术跟上发展步伐中所扮演的关键角色等方面，深入探讨这个问题。
Harry Chen（陈海力）自2008年加入联发科（MediaTek），目前担任IC测试科学家，通过与学术界的合作研究，探索先进的设计与测试方法。他的研究兴趣包括缺陷建模、通过数据分析进行后硅品质分析，以及系统级测试（SLT）。他已发表多篇论文，并在IEEE会议上发表演讲。他同时担任VLSI-DAT设计自动化与测试方法学委员会共同主席，以及亚洲及南太平洋设计自动化会议（ASP-DAC）和国际测试会议（ITC）技术委员会成员。此外，他也是SEMI台湾测试委员会共同主席，并领导IEEE异质整合蓝图（HIR）测试技术工作小组的SLT分组。在加入联发科之前，Harry曾任职于Analog Device（ADI）担任资深工程师，负责行动电话系统单晶片的整合实现（8年）。在ADI之前，Harry于电子设计自动化（EDA）领域工作14年，于Cadence Design Systems及两家后来被Cadence收购的EDA初创公司，开发IC测试自动化工具。Harry分别于麻省理工学院（MIT）及斯坦福大学取得电机工程学位。
Harry Chen has been with MediaTek since 2008 currently holding the position of IC Testing Scientist investigating advanced design and test methodologies through collaborative research with academia. His interests include defect modeling, post-silicon quality analysis via data analytics, and system-level test (SLT). He has published numerous papers and given talks at IEEE conferences. He serves as Co-Chair of Design Automation and Test Methodology committee of VLSI-DAT and on technical program committees for Asia and South Pacific Design Automation Conference (ASP-DAC) and International Test Conference (ITC). Additionally, he is Co-Chair of SEMI Taiwan Testing Committee and leads IEEE Heterogeneous Integration Roadmap (HIR) Test Technology Working Group's SLT Section. Prior to MediaTek, Harry was a staff engineer at Analog Devices (ADI) working on mobile phone system-on-chip integration and implementation (8 years). Prior to ADI, Harry spent 14 years in electronic design automation (EDA) developing IC test-automation tools at Cadence Design Systems and two EDA start-ups that were acquired by Cadence. Harry obtained electrical engineering (EE) degrees from Massachusetts Institute of Technology (MIT) and Stanford University.
“集成电路测试设备稳定性预测评估补偿方法研究 ”
Abstract - Biography (English)
The complexity of integrated circuits (ICs) continues to escalate, accompanied by simultaneous enhancements in performance. The stability of IC testing equipment is a critical factor in ensuring IC quality and production efficiency. Traditional methods for predicting IC testing equipment stability exhibit certain shortcomings in anomaly detection, often relying on offline maintenance, which not only hampers production efficiency but also makes it difficult to promptly identify equipment anomalies. Noise introduced by unstable equipment can interfere with the consistency of test results, leading to reduced yield. Conventional error compensation methods fail to meet real-time requirements, resulting in diminished efficiency and thereby limiting improvements in IC testing equipment performance and the fulfillment of practical application demands. To overcome these limitations, this paper proposes the following three methods for the prediction, evaluation, and compensation of IC testing equipment stability:
- Recognizing the inadequacy of traditional stability prediction methods in identifying anomalous test results, this study proposes a method that leverages the upper confidence limits of a normal distribution. The approach employs the K-Medoids clustering algorithm to classify sample data, compares the accuracy of upper confidence limits under two common confidence levels, selects the more accurate one as the threshold, and then identifies and flags non-compliant test data based on predefined qualification criteria. Experimental results demonstrate that this method enables qualitative stability analysis of IC testing equipment through quantitative thresholds, allowing for more precise prediction of potential anomalies during testing and providing effective foresight into the long-term stable operation of IC testing equipment.
- To address the efficiency decline caused by traditional periodic offline maintenance of IC testing equipment, this study proposes the SWAQ comprehensive analysis model, which integrates Spearman Rank Correlation Coefficient Analysis (SRCCA), Weighted Average Method (WAM), and Quadrant Analysis (QA). The model first calculates the weights of test items using Spearman rank correlation analysis while eliminating redundant test items. It then computes the weighted average yield and weighted CPK (Process Capability Index) for each batch of ICs, generating a quadrant distribution chart for real-time comprehensive assessment of IC quality and process stability. Experimental results demonstrated that the SWAQ model exhibits significant advantages in real-time assessment, weight allocation, response time, and maintenance cycles. Redundant test items can be effectively identified, and weights can be reasonably assigned to accurately distinguish performance differences among batches. Traditional periodic maintenance is transformed into on-demand maintenance, leading to improved evaluation efficiency and precision, and enhancing the reliability of the equipment.
- Given the impact of noise during unstable phases of IC testing equipment and the poor real-time performance of traditional error compensation methods, this study proposes a real-time compensation method based on Particle Swarm Optimization (PSO)-enhanced Kalman Filtering (KF). This approach dynamically optimizes the noise parameters of KF using the PSO algorithm, enabling KF to adapt to dynamic noise variations. It also performs real-time analysis and compensation of test results during IC testing. In the experimental section, this paper verifies the compensation effectiveness separately for current and voltage test items, and compares the PSO-KF algorithm with the non-optimized KF algorithm as well as KF algorithms optimized by Genetic Algorithm (GA) and Ant Colony Optimization (ACO). The results indicate that the PSO-KF algorithm outperforms the other methods in all aspects, demonstrating superior stability and anti-interference capability. After compensation, the yield rates of current and voltage tests increased by 1.389% and 0.385%, respectively, achieving an improvement in IC testing quality and significantly enhancing IC testing reliability.
摘要 - 简介 (Chinese)
集成电路（Integrated Circuits, IC）的复杂程度日益攀升，其性能也在同步增强，IC测试设备稳定性是保障IC质量与生产效率的核心要素，传统的IC测试设备稳定性预测方式在异常数据分辨方面有一定缺陷，普遍借助离线维护，这不仅对测试效率造成损害，而且不易及时察觉设备异常。不稳定设备携带的噪声会干扰测试结果的稳定性，引起测试良率降低情况的出现，传统误差补偿方法的实时性未满足既定水平，引起效率减退，进而在IC测试设备性能的提升及实际应用需求实现方面受到限制，为缓解上述局限，本文针对IC测试设备稳定性的预测、评估和测试结果的补偿，提出了以下三个方法：
- 鉴于传统IC测试设备稳定性预测方法识别测试结果异常能力存在缺陷，提出基于正态分布上侧界值对设备稳定性予以预测的方法。此方法依靠K-Medoids聚类算法对样本数据进行分类考察，比较两个常见置信度对应的上侧界值准确程度大小，把准确度较高的那个选作阈值，接着根据合格界限，鉴别不合格测试数据继而报警输出。实验结果说明，此方法借助定量阈值完成对IC测试设备稳定性的定性分析，能更精准地预测测试中可能出现的异常情况，实现对IC测试设备长期稳定运行情形的有效预测。
- 针对传统IC测试设备因开展定期离线维护造成效率下滑这一问题，提出了一种基于斯皮尔曼秩相关系数分析（Spearman Rank Correlation coefficient analysis, SRCCA）、加权平均法（Weighted Average, WAM）、四象限图（Quadrants Chart, QC）的SWAQ综合分析模型。此模型首先借助斯皮尔曼秩相关系数分析方法算出各测试项权重，同时把冗余测试项去除掉，随后求出各批次IC加权良率均值及加权CPK（过程能力指数，Process Capability Index）均值，生成四象限分布图以对各批次IC质量和过程稳定性做实时综合判断。实验结果表明，SWAQ模型在实时评估、权重分配、响应时间和维护周期等方面具有显著优势，能够有效识别冗余测试项目并合理分配权重，准确区分批次之间的性能差异，把先前的定期维护转变为按需保养，促进了评估效率与精准水平提升，增进了设备的可靠性。
- 鉴于IC测试设备不稳定阶段噪声对结果稳定性形成的影响，以及传统误差补偿方法实时表现的状况较差，提出一种基于PSO（Particle Swarm Optimization, PSO）优化卡尔曼滤波（Kalman filtering, KF）的实时补偿方法。这种模式使用PSO算法对KF的噪声参数实施动态优化，使KF可达成适应噪声动态变化的效果，还在IC测试期间针对测试结果开展实时分析与补偿。在实验部分，本文分别对电流和电压测试项进行补偿效果验证，并将PSO-KF算法与无优化的KF以及遗传算法（Genetic Algorithm，GA）、蚁群优化算法（Ant Colony Optimization, ACO）优化的KF进行对比。结果表明，PSO-KF算法在各方面均优于其他方法，具有更强的稳定性和抗干扰能力。补偿后，电流和电压测试的良率分别提高了1.389%和0.385%。实现了IC测试质量的提升，切实增强了IC测试的可靠性。
“芯片测试解决方案满足 224 Gbps PAM4、高功率和高引脚数要求”
Abstract - Biography (English)
Abstract
High-speed, high-power, high-pin-count ICs are typically found in advanced applications requiring significant processing power and data transfer rates, such as high-performance computing, data centers, and advanced networking. These ICs often utilize advanced packaging techniques and specialized sockets to handle the increased complexity and thermal requirements.
Key Characteristics:
- High Speed: These ICs operate at very high frequencies, enabling rapid data processing and transmission, up to 224Gbps PAM4 requirement.
- High Power: They require significant electrical power to function, leading to thermal management challenges.
- High Pin Count: They have a large number of input/output (I/O) pins, facilitating complex connections and data paths, as well as high warpage challenge.
Test Solutions:
Testing these complex ICs requires advanced test systems with high speed, high current capacity, and enhanced thermal dissipation for high-power requirements.
This paper will introduce how Smiths tackle these high-speed, high-power, high-pin-count test requirements.
Biography
Frank Liu
Sr. Engineering Manager, SEMI BU
Frank Liu graduated from Shandong University of Science and Technology in 2001, majoring in Mechanical design and manufacturing. He studied for his MBA at Tongji University in 2018. Frank Liu started working in Smiths Interconnect Suzhou in 2007, and now he is Sr. Engineering Manager for Semi test product development.
摘要 - 简介 (Chinese)
高速、高功率、高引脚数的集成电路 (IC) 通常用于需要强大处理能力和数据传输速率的高级应用，例如高性能计算、数据中心和网络传输。这些集成电路通常采用先进的封装技术和专用的芯片测试座和测试方案来应对日益增长的复杂性和散热要求。
主要特性：
- 高速：这些集成电路工作频率极高，可实现高达 224Gbps PAM4 的快速数据处理和传输。
- 高功率：它们需要极大的功率才能运行，从而带来散热管理方面的挑战。
- 高引脚数：它们具有大量的输入/输出 (I/O) 引脚，使得连接和信号路径更加复杂，同时也带来了严重的翘曲问题。
测试解决方案：
测试这些复杂的集成电路需要先进的测试解决方案，该系统具有高速、高电流和增强的散热性能，以满足高功率要求。
本文将介绍史密斯公司如何应对这些高速、高功率、高引脚数的测试挑战。
个人简介
刘德先
资深工程研发经理，SEMI BU
刘德先，2001年毕业于山东科技大学，所学专业是机械制造工艺与设备专业。2018年参加同济大学的工商管理硕士(MBA)的学习。自2007年起，刘德先就职于史密斯英特康苏州，目前任职资深工程研发经理负责半导体测试产品研发。
15:15
Posters & Networking
Enjoy time to meet with the presenters and network while refreshments are served.“车规级高压待测器件电源 IC”
Abstract - Biography (English)
Elevate Semiconductor’s Whitney is a two-channel high voltage parametric measurement unit System-on-a-Chip designed for rigorous testing of automotive-grade semiconductors operating up to 100V and beyond.
It supports advanced four-quadrant testing through a stackable architecture with pseudo floating ground feature that enables voltages suitable for modern electric vehicles, maintaining 0.05% measurement accuracy with six integrated 16-bit DACs per channel and high-speed SPI interface to reduce test time.
Whitney facilitates comprehensive qualification of high reliability automotive ICs across extended voltage ranges, ensuring component reliability for evolving high-voltage automotive platforms while supporting efficient manufacturing throughput.
摘要 - 简介 (Chinese)
Elevate Semiconductor 的 Whitney 是一款双通道高压参数测量单元系统级芯片（System-on-a-Chip），专为严苛的车规级半导体测试而设计，工作电压可达 100V 甚至更高。
它支持通过可堆叠架构进行先进的四象限测试，并具备伪浮地功能，使其能够输出适用于现代电动汽车的电压。Whitney 在每个通道中集成了六个 16 位 DAC，测量精度可达 0.05%，并配备高速 SPI 接口以缩短测试时间。
Whitney 有助于对高可靠性车用 IC 进行全面的鉴定测试，覆盖扩展电压范围，确保元器件在不断发展的高压汽车平台中的可靠性，同时支持高效的制造产出。
“同轴测试插座中的弹簧探针载流能力研究”
Abstract (English)
Abstract
With the development of AI and automated driving technology, the chip develops towards high power. During the IC test by test socket, there are high currents through the probes. Typically, multiple probes are used to distribute the high power, ensuring that the current flowing through each probe remains below its current capacity. When such high currents pass through these probes, heat is generated due to the thermoelectric effect. This causes localized temperature increases inside the socket, reducing the current-carrying capacity of the probes at that location.
To assess the probe temperature and current impact in DaVinci Co-axial, we conducted experiments and simulation to infer real testing probe temperature. In this study, all probes are connected in series within the test fixture by a PCB and supplied with a constant current. A thermocouple is used to measure the center probe temperature. The temperature of the PCB is controlled to simulate the operating environment temperature of the chip. The simulation result meets the validation result, which gives us confidence to use the method for real product simulation.
摘要 (Chinese)
随着人工智能和自动驾驶技术的发展，芯片正朝着高功率方向发展。在集成电路（IC）测试中，测试插座会通过探针传输高电流。通常会使用多个探针来分配高电流，以确保流经每个探针的电流不超过其电流容量。当如此高的电流通过这些探针时，由于热电效应会产生热量。这会导致插座内部局部温度升高，从而降低该位置探针的载流能力。
为了评估 DaVinci Co-axial 中探针的温度和电流影响，我们进行了实验和模拟，以推断真实的测试探针温度。在本研究中，所有探针通过印刷电路板（PCB）在测试夹具内串联连接，并供应恒定电流。使用热电偶测量中心探针的温度。控制 PCB 的温度以模拟芯片的工作环境温度。模拟结果与验证结果一致，这使我们相信该方法可用于真实产品的模拟。
16:00
“先进的导热性能：下一代 Pattern X —— 用于翘曲和不平表面的可压缩金属导热界面材料”
Abstract - Biography (English)
Thermal interface materials (TIMs) are critical for heat dissipation in electronic applications. With the thermal management market projected to exceed $1 billion, innovation in TIMs is accelerating—especially for high-performance computing, automotive electronics, and power semiconductors. Traditional materials like thermal pastes, phase change materials (PCMs), graphite sheets, and metal-based TIMs have served well, but rising power densities and AI workloads are testing their limits.
A key advancement in this field is the compressible metal TIM known as “Heat-Spring®.” Along with this, a novel “Next-generation Pattern X” compressible TIM represents a breakthrough in performance and mechanical compliance.
Next-generation Pattern X is composed of pure indium—a soft, highly-conductive metal—delivering excellent thermal transfer and low contact pressure (~30 psi), ideal for warped or delicate surfaces. It avoids common polymer-based TIM failures such as pump-out and bake-out and is reworkable—offering added flexibility and cost efficiency.
Next-generation Pattern X is applied through simple mechanical compression, eliminating the need for reflow. Its design features a higher, more compressible pattern compared to other Heat-Spring® patterns, making it particularly effective for non-planar surfaces. Warped surfaces have historically posed challenges for solid metal TIMs, but Next-generation Pattern X’s advanced patterning enhances its conformance and performance in such applications. This makes it especially suited for assemblies with high coefficients of thermal expansion (CTE) mismatch or curved substrates.
In internal testing, Next-generation Pattern X was evaluated on a 20 x 25 mm die with 125 µm crown warpage under power cycling up to 1,400 watts. Results demonstrated consistently lower and more uniform junction temperatures across the die, even under extreme thermal and mechanical stress. This level of thermal consistency is essential for device reliability and yield in advanced semiconductor packaging.
Next-generation Pattern X’s combination of performance, compliance, and simplicity makes it suitable for a wide range of applications, including TIM1.5 (between chip and lid), TIM2 (lid to cold plate), IGBT modules, liquid immersion cooling, burn-in, system-level testing, and functional reliability tests.
As electronic systems continue to evolve toward higher power densities and more complex packaging, compressible metal TIMs like Next-generation Pattern X are emerging as essential solutions. With its unique ability to manage thermal challenges on warped or non-planar surfaces, Next-generation Pattern X sets a new benchmark in reliable, high-performance thermal interface design.
Foo – Assistant Product Manager, Indium Corporation
- Recognized expert in Thermal Interface Materials, driving innovative solder-based TIM solutions across Asia.
- Over 12 years at Huawei Technologies as a Quality Manager, leading product reliability and quality initiatives. Former Quality & Reliability Engineer at Avago Technologies (now Broadcom), supporting high-performance semiconductor products.
- Trusted trainer delivering impactful technical & commercial insights to customers and partners.
- Accredited Six Sigma Green Belt.
- B.Eng. (Hons) in Electronics Engineering, Multimedia University, Malaysia.
摘要 - 简介 (Chinese)
导热界面材料（TIM）在电子应用的散热中至关重要。热管理市场预计将超过 10 亿美元，同时 TIM 的创新，尤其是在高性能计算、汽车电子和功率半导体等领域的创新正不断加速。传统材料如导热硅脂、相变材料（PCM）、石墨片以及金属类 TIM 虽然表现良好，但随着功率密度和 AI 负载的上升，其性能已逐渐逼近极限。
该领域的一项关键进展是可压缩金属 TIM——“Heat-Spring®”。在其基础上，创新性的“下一代 Pattern X”可压缩 TIM 实现了性能和力学适应性的重大突破。下一代 Pattern X 由纯铟制成。铟是一种柔软且高导热的金属，能够在低接触压力（约 30 psi）下实现优异的导热性能，非常适合翘曲或脆弱的表面。它避免了常见的聚合物类 TIM 故障，例如泵出（pump-out）和烘烤失效（bake-out），并且可返修，提供更高的灵活性和成本效益。
下一代 Pattern X 通过简单的机械加压即可应用，无需回流工艺。相比其他 Heat-Spring® 型号，Pattern X 的设计起伏更高且更易压缩，使其在非平面表面上的表现尤为突出。翘曲表面对固态金属 TIM 一直是重大挑战，而 Pattern X 的先进设计显著提升了其贴合性和性能。这使其特别适用于存在高热膨胀系数（CTE）失配或曲面基板的组装应用。
在内部测试中，采用 20 x 25 mm 且翘曲度高达 125 μm 的芯片对下一代 Pattern X 进行了 1,400 瓦的功率循环测试。结果显示，即使在极端的热与机械应力下，芯片仍保持更低且分布均匀的温度。这种热一致性对于先进半导体封装中的器件可靠性与良率至关重要。
凭借更好的性能、可塑性和易操作性，Pattern X 可适用于广泛的应用场景，包括 TIM1.5（芯片与盖板之间）、TIM2（盖板到冷却板）、IGBT 模块、液体浸没冷却、预烧测试、系统级测试以及功能可靠性测试。随着电子系统不断向更高功率的密度和更复杂的封装发展，像 Pattern X 这样的可压缩金属 TIM 正逐渐成为极其重要的解决方案。其独特的能力能够有效应对翘曲或非平面表面的热管理挑战，为可靠的高性能热界面设计树立了新的标杆。
在热界面材料领域的公认专家，负责全亚洲的创新焊料型 TIM 解决方案的推广和应用。
- 在华为技术有限公司工作超过 12 年，担任质量经理，主导产品可靠性与质量改进。曾任安华高科技（现博通）质量与可靠性工程师，支持高性能半导体产品。
- 为客户和合作伙伴提供技术与商业应用相关的培训。
- 拥有六西格玛绿带认证。
- 马来西亚 Multimedia University 电子工程荣誉学士。
在热界面材料领域的公认专家，负责全亚洲的创新焊料型 TIM 解决方案的推广和应用。
- 在华为技术有限公司工作超过 12 年，担任质量经理，主导产品可靠性与质量改进。曾任安华高科技（现博通）质量与可靠性工程师，支持高性能半导体产品。
- 为客户和合作伙伴提供技术与商业应用相关的培训。
- 拥有六西格玛绿带认证。
- 马来西亚 Multimedia University 电子工程荣誉学士。
“ 基于低带宽模板的 UWB 频谱测试超低成本解决方案 ”
Abstract - Biography (English)
Abstract
USB (Ultra Wideband) is becoming a very amusing technology. It is not only widely used in the indoor position with very good precision, speed and reliability, but also used for low power and short-range radio communication applications with fast and stable date rate.
The most UWB will operate on the sharing spectrum with other license and un-license application, so UWB applications is always put under surveillance of the spectrum in order to avoid the radio interference. And UWB industry alliance had made the strict rules and test specification. One test items of the test specification is the spectrum mask. And most of the UWB applications has more than 500MHz bandwidth, and their spectrum mask will require test more than 800MHz bandwidth. At present, There is an available WSWB test solution for the UWB spectrum mask testing in the V93000, and it is a too expensive test solution to use in the mass production.
This paper will present a very low cost test solution with WSRF. And the WSRF measurement bandwidth is only 200MHz, how to measure the UWB spectrum mask with WSRF is a big challenge for us. And this paper will give an implementable test solution with under-sampling method and get the reasonable results. And in the lab, we will use the WSWB to stimulus the UWB signal and use WSRF to measure the UWB spectrum mask, and demonstrate my lab results.
At last I gave the compared UWB spectrum mask results between the WSRF and WSWB. Compared with WSWB test solution, WSRF UWB spectrum mask test solution is easy to implement with high site count parallel testing, it will significantly decrease the test cost. And our lab results has proved the WSRF test solution on UWB spectrum mask is a very low cost and reliable test solution.
Biography
Yongjun Hu
Senior Consulting Manager
Yongjun Hu, currently working in the SOC Business Development and COE center of ADVANTEST (China), is engaged in the application development of 5G, transceiver, RF front end and mmWave segment ATE test solutions. He has more than 16 years of working experience in the RF and anolog testing field in semiconductor industry, and about 10 years of working experience in RF design, debug and system architecture for communication and radar before joining Verigy (now Advantest) semiconductor testing industry.
摘要 - 简介 (Chinese)
摘要
超宽带技术正在成为一个很有吸引力的技术，它不仅被广泛应用于室内和室外，具有很好的精度、速度和可靠性，而且还用于低功耗和短距离无线电通信应用，具有快速和稳定的数据速率。
超宽带技术（UWB）通常与其他授权及非授权的应用共享频谱资源，因此其应用始终处于频谱监控之下以避免无线电干扰。UWB行业联盟已制定严格规范与测试标准，其中频谱模板测试是其中的核心指标之一。由于多数HRP UWB应用带宽超过500MHz，其频谱模板测试需覆盖800MHz及以上的带宽范围。目前V93000平台虽具备可用的超宽带频谱模板测试方案，但该方案成本过高，难以应用于量产场景。
本文将提出一种基于WSRF的低成本测试方案。由于WSRF的测量带宽仅有200MHz，如何用它来测量UWB频谱模板成为一个的重大挑战。为此我们开发了可实施的欠采样测试方案，并获得了合理有效的测量结果。在实验中，我们采用WSWB信号激励UWB设备，并通过WSRF进行频谱模板测量，最终展示了实验室的实验成果。
最后对比了WSRF与WSWB的频谱模板测量结果。相较于WSWB方案，WSRF的UWB频谱掩模测试方案不仅易于部署，还能实现多站点并行测试，显著降低测试成本。我们的实验数据充分证明，WSRF在UWB频谱模板测试中的应用方案具有低成本和高可靠性双重优势。
最后，还提供了爱德万测试最新的WSRF20ex的测试方案，它是公司官方推荐的超宽带测试方案，它具有测试设置简单，有一套专门的API可供用户使用。不仅可以完成频谱模板测试，还可以完成NMSE测试和其他的UWB常用的测试。
个人简介
胡拥军
高级顾问经理
现任爱德万（中国）管理有限公司，在事业部业务发展与专家中心（COE），专注于5G、收发器、射频前端及毫米波段ATE测试解决方案的技术研发工作。他已在射频与模拟测试领域深耕16年；在加入惠瑞捷（现爱德万）半导体测试行业前，已经拥有约10年通信与雷达的射频设计，调试及系统架构经验。
“可扩展集成固件映像协调器在Intel聊天机器人中的应用”
Abstract - Biography (English)
Abstract
The Integrated Firmware Image (IFWI) is a critical component in ensuring the functionality and stability of Intel hardware systems. It comprises various sub-components such as BIOS, CSME, PMC, GbE, and ucode, which require precise version pairing for optimal performance. Traditionally, extracting and modifying IFWI data necessitated the use of different multiple tools, each requiring separate setup and installation. This project introduces a scalable IFWI Orchestrator integrated into Intel's AI chatbot, Quality Information Response Interface (QIRI), allowing users to efficiently select and utilize IFWI-related tools for information extraction and modification.
The primary objective of this project is to streamline the process of accessing and utilizing IFWI tools through Intel's chatbot, also known as Quality Information Response Interface (QIRI). By integrating these tools into the chatbot, users can quickly and easily extract necessary information from IFWI or modify its internal values without extensive setup procedures.
The integration of IFWI Tools, such as Intel Image Analyzer (IIA) and BIOS Knob Adjuster, leverages QIRI’s Databroker architecture to facilitate user interaction with IFWI-related issues. The chatbot serves as a front-end interface, identifying user intent and directing requests to the IFWI Orchestrator hosted on a separate server. Communication between the chatbot and the backend server is managed using ActiveMQ. The IFWI Orchestrator automates tool execution and returns extracted results to the chatbot, with file output stored in MongoDB for user retrieval if they so desire.
The IFWI Orchestrator's scalability promises future enhancements, including additional tools and improved analysis pipelines, enabling users to seamlessly transition between applications within the chatbot interface. This innovative approach provides Intel users with round-the-clock access to IFWI tools via Microsoft Teams, significantly improving the efficiency and effectiveness of firmware image management.
Biography
Chongyuan Lv
Senior Software Enabling and Optimization Engineer
Chongyuan Lv is senior Software Enabling and Optimization Engineer at Intel. He has 15 years of firmware/BIOS development and customer support experience, covering Intel's Xeon platform in the server field, and the Core/Ultra platform in desktop and notebook areas. Currently, he is in the CCG China Edge Customer Engineering team, primarily responsible for collaborating with customers to evaluate the use of Intel's latest platforms in customer projects and providing full-stage support from project initiation to launch. Additionally, he is responsible for promoting the implementation of various firmware solutions based on Intel platforms in customer projects, such as UEFI and SBL (Slim Boot Loader), etc.
摘要 - 简介 (Chinese)
摘要
集成固件镜像（IFWI）是确保 Intel 硬件系统功能性与稳定性的关键组件。它由多个子组件组成，如 BIOS、CSME、PMC、GbE 和 ucode，这些组件需要精确的版本配对以实现最佳性能。传统上，提取和修改 IFWI 数据需要使用多个不同的工具，每个工具都需单独安装和配置。本项目引入了一个可扩展的 IFWI Orchestrator，并将其集成至 Intel 的 AI 聊天机器人——质量信息响应接口（QIRI）中，使用户能够高效地选择和使用与 IFWI 相关的工具，以进行信息提取与修改。
本项目的主要目标是通过 Intel 的聊天机器人（即质量信息响应接口 QIRI）简化访问和使用 IFWI 工具的流程。通过将这些工具集成到聊天机器人中，用户可以快速、便捷地从 IFWI 中提取所需信息，或修改其内部参数，而无需繁琐的安装和配置过程。
集成 IFWI 工具（如 Intel 图像分析器 IIA 和 BIOS 参数调节器）充分利用 QIRI 的 Databroker 架构，促进用户与 IFWI 相关问题的交互。聊天机器人作为前端界面，负责识别用户意图，并将请求转发至部署在独立服务器上的 IFWI Orchestrator。聊天机器人与后端服务器之间的通信通过 ActiveMQ 管理。IFWI Orchestrator 自动执行工具操作，并将提取结果返回至聊天机器人，同时将文件输出存储在 MongoDB 中，供用户按需检索。
IFWI Orchestrator 的可扩展性为未来的功能增强提供了可能，包括新增工具和优化的分析流程，使用户能够在聊天机器人界面中无缝地在不同应用之间切换。这一创新方法使 Intel 用户能够通过 Microsoft Teams 全天候访问 IFWI 工具，显著提升了固件镜像管理的效率与效果。
个人简介
侣重远
高级软件使能和优化工程师
侣重远是来自英特尔的高级软件使能和优化工程师，有15年的固件开发和客户支持经验，涵盖了英特尔的服务器领域的Xeon平台，台式机笔记本领域的Core平台。目前在英特尔边缘计算客户工程团队，主要负责和客户一起合作评估英特尔最新平台在客户项目中的使用，并全阶段支持客户项目从立项到发布，另外负责推广基于英特尔平台的不同固件解决方案在客户项目中的落地，如UEFI，SBL(SlimBootLoader)等。
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