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Tutorial – Package Test is a Dirty Business !!!
"Package Test is a Dirty Business !!!
Socket Cleaning Strategies to Reduce Cost of Test and Improve Overall Equipment Effectiveness (OEE)"
Jerry Broz, Ph.D.
VP World Wide Applications, International Test Solutions
Part One
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Part Two
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Abstract
During assembled device testing with new socketing solutions, the connectors are clean and have stable resistance values. With continuous testing, contamination accumulated within the socket and materials are transferred to the contactor. Sources of resistive contamination are numerous and may include oxides, accumulated metals, residues from processing, or debris from the test environment. Over time, these adherent materials will form non-conductive “layers” that dramatically affect the electrical performance of the contactor. Experience has shown that over 70% of device yield fallout and re-screen can be attributed to electrical contact related issues.
To avoid multiple rescreen resulting in increased Cost of Test (COT), sockets have been historically maintained with various off-line cleaning practices combined with frequent pin replacement. Clearly off-line methods reduce throughput and increase tool downtime, so socket makers and pin designers have focused on robust technologies (e.g., tip geometries, platings, alloys, etc.).
In recent years, the major handler suppliers have developed tools with programmable auto clean functionalities capable of regular socket cleaning without substantial downtime. Such improvements in test infrastructure are critical for lowering COT and the recent developments support this trend.
In this broad tutorial, various off-line and on-line socket cleaning practices will be surveyed and discussed. High volume testing challenges and solutions for on-line cleaning to maintain high yield and throughput, reduce socket repairs, and control contactor damage will be covered. Key information regarding the auto clean functionalities from the major handler suppliers as well as recommendations for implementation will be presented and several case studies will be reviewed.
Biography
Jerry Broz, Ph.D., has been the Applications Engineering Team Leader and VP of Applications at International Test Solutions since 2003. Dr. Broz is responsible for the ITS branch office teams located in Taiwan, Korea, Japan, China, and Singapore that are focused on optimal on-line cleaning solutions for wafer sort and package test. Previously, Dr. Broz was a Member of Technical Staff with the Worldwide Probe Development Team at Texas Instruments, Inc. He has authored numerous publications and presentations in the areas of wafer level test, package test, and IC packaging. Dr. Broz holds a number of US and International patents as well as several pending patent applications related to wafer sort, package test, and front-end processes. Dr. Broz earned a Ph.D. in Mechanical Engineering from the University of Colorado at Boulder and has over 20 years of experience in various high volume manufacturing and applied research environments. Dr. Broz is the General Chair for IEEE SW Test Workshop and a Sr. Member of the IEEE as well as an IEEE Golden Core member.
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