TechTalk – Thermal and Mechanical Challenges for Test Handlers

Welcome!

To access the archive contents (presentation slides, videos, multimedia, etc.) sign in using your LinkedIn account by clicking the LinkedIn button to the right. Full Conference Attendees and Subscribers have access to all content now. FREE guests, once signed in, have access to the presentations after June 1, 2013.

------ This message is only displayed when you are not signed in. ------

TechTalk – Thermal and Mechanical Challenges for Test Handlers

"Thermal and Mechanical Challenges for Test Handlers"
Jerry Tustaniwskyj, Ph.D.
Director of Technology Development, Delta Design, Inc.

Part One

Video Player Goes Here

Sorry, you do not NOT have access to this file.

Part Two

Video Player Goes Here

Sorry, you do not NOT have access to this file.

Part Three

Video Player Goes Here

Sorry, you do not NOT have access to this file.

Abstract
IC devices continue to evolve with higher functionality and lower cost. This higher functionality means that the device circuit density is increased as is the corresponding number of IO’s. The overall size of these devices is decreasing in order to improve performance and be useable in applications with minimal space such as mobile phones or tablets. These devices include multi-chip modules, 3-D packages, lapped silicon with thinned substrates, etc. In order to continue to drive device costs lower, these more complex devices cannot increase test time, resulting in a real push to increase the parallelism of test. Unique new challenges exist for test handlers with these devices during functional test as well as for other test processes such as burn-in or system level test.

This seminar addresses a number of challenges related to testing these devices. These challenges include purely mechanical issues as well thermal. We discuss the need for more robust pick and place processes along with the precision alignment of the device under test (DUT) to the contact pins. The use and advances of vision systems are described. Their benefit is not only in device alignment, but also for process control and diagnostics. We review the material property and thermal expansion issues related to testing at extreme temperatures (tri-temp).

A considerable portion of the seminar is dedicated to thermal control of the DUT. Traditional methods need to be modified in order to control device temperature with the new packaging technologies. We discuss the thermal challenges of designing highly parallel passive systems along with active thermal control for each DUT. Cost versus performance tradeoffs are addressed for both low and high power dissipating devices as well as the pros and cons of air, liquid, phase change, and thermoelectric cooling systems.

We also have included a brief discussion on requirements for testing MEMS devices, where in addition to electrical test, physical excitation of the device is required.

Biography
Jerry Tustaniwskyj, Ph.D. earned a Bachelor of Science and a Ph.D. in Mechanical Engineering from Wayne State University. He has been the Director of Technology Development at Delta Design, Inc. since 2006. From 1973 through 2006 he held a range of positions from engineering intern to Unisys Fellow, involved with mechanism design, controls, thermal systems, device packaging, at Burroughs/Unisys. His academic experience includes serving as an Assistant Professor of Mechanical Engineering at Wayne State University from 1975 – 1976 and from 1986 to the present as a part time faculty member in Mechanical and Aerospace Engineering (MAE) at the University of California, San Diego. Dr. Tustaniwskyj has 47 issued patents, 3 patent applications pending and 16 technical publications. From 2004 to the present he has served as an evaluator (representing ASME) of university mechanical engineering programs for ABET (Accreditation Board for Engineering and Technology).

 

Return to the 2013 BiTS Workshop Archive index page