Call For Presentations & Posters for

Hilton Phoenix / Mesa Hotel - Mesa, Arizona

TestConX is seeking presentation and poster proposals on a broad range of test and burn-in topics.

Each presentation at TestConX is provided a thirty minute presentation slot (approximately 25 minutes for the presentation with 5 minutes for questions and answers). Authors only need to prepare a PowerPoint presentation. (There is no paper to write.)

Posters are three oversized 24" W x 36" H pages which are displayed during an interactive session with the attendees.

Presentations and Poster final submissions are due in mid-January.

Please submit a 250 to 500 word abstract for presentations or posters of your original, previously unpublished, technical presentation by .

Submit via:

Abstracts will be reviewed and authors will be notified around .

Topics of interest include, but are not limited to:

Electrical & Mechanical Challenges
  • Wafer Level Packages, Thinner Packages & Package-on-Package (PoP)
  • Design tools: geometric dimensioning and tolerancing (GD&T); finite element analysis (FEA), etc.
  • Ball deformation & package stress
  • Package alignment
  • High frequency and high data rate techniques and technologies (AI, 5G, IOT test, SERDES, PA test, A/D test)
  • Power management IC testing
  • Final test and probe convergence
  • High current, high power, and/or high temperature device testing
  • Handler & change kit designs and considerations
  • Managing ESD
  • Fine Pitch Kelvin Contacting
  • Automotive semiconductor requirements
  • Thermal management and modeling
  • Voltage and current extremes, high and low
Printed Circuit Board (PCB) Design & Manufacturing
  • High temperature Burn-in board applications
  • High current and high power support
  • Trade-offs: Power delivery vs Inductance
  • Advanced materials for high speed, high data rate, or power management
  • RF and low loss materials
  • Copper foil surface roughness
  • High data rate test applications
  • Space Transformers
  • Ultra-fine pitch
  • Board to Board Interconnects
  • Coefficient of thermal expansion (CTE), force, & planarity issues
  • Temperature/Humidity/Bias (THB), highly accelerated stress test (HAST) or other special applications
  • Printed electronics
Advanced Packaging Technologies
  • PoP, Bare Die, system on a chip (SOC), and 3D package testing
  • Wafer level chip scale (WLCSP) test for Known Good Die (KGD) or final test
  • Minimizing metals & plating of material
  • Low power and/or alternative power
  • Lead-Free
  • Interconnect solutions for photovoltaic products
  • Fan out, fan in wafer level and panel level packaging
Test Process & Operational Challenges
  • Test & burn-in floor operations
  • Socket repair, cleaning, and re-plating methods
  • Value Engineering: methods and techniques for reducing cost of ownership, achieving low-cost burn-in,etc.
  • Massively parallel and non-singulated test
  • Test strategies for reducing qualification and production time
  • Socket & PCB verification, checkout & qualification
  • Test-in-Tray
  • High reliability testing for mission critical and medical applications
  • Microelectromechanical system (MEMS) and non-electrical (optical, fluidic, magnetic, acoustic, etc.) stimuli or response testing
  • Factory automation
Material Challenges
  • Contact technology: dissimilar metal interface degradation, carbon nanotube developments, non-traditional interface materials, contact reliability in test and burn-in conditions
  • Various plating and surface finish impact
  • Metal (contact), plastic (housing), ceramic (package/substrate) and composite behavior in test environment.
  • Reducing/recycling materials used in shipping sockets, PCBs and other products
Next generation Test Cell/Test Operations
  • Test requirements, set up
  • Integration with various thermal hardware
  • Test program/Data analysis
  • Panel processing & handling
  • Strip Testing
  • Validation, Bring up, System Level Testing
  • Product/Module level testing
Advanced Manufacturing Challenges
  • PCBs, Socket housing, Contact technologies
  • 3D printing applicable to test cell
  • Additive manufacturing/nanotechnology applied to test hardware/process
  • Cradle to cradle manufacturing
mmWave Testing
(5G, WiGig, …)
  • Contacter technologies
  • PCB / DUT Board Design, PCB Characterization, Port Aggregation
  • Over-the-air testing
  • Test Strategies, Correlation, Applications
  • Test Requirements and Test Solutions

As an Author you’ll contribute to a stimulating and comprehensive technical program by sharing your latest work and advancements with colleagues from around the globe. Whether you’ve previously made a podium or poster presentation at TestConX, or are considering becoming an author for the first time, we encourage and welcome you to submit an abstract for your proposed presentation or poster.

TestConX is the world’s premier event for test engineering and operations dedicated to providing a forum for the latest information on a broad range of topics related to electronic test. Focused on "connecting electronic test professional to solutions", the technical program provides pratical content that is immediately useful. TestConX is the place where industry colleagues from around the world come to learn from presentations made by people like you!

For additional questions and other inquiries please contact: