{"id":60,"date":"2013-03-06T10:05:56","date_gmt":"2013-03-06T18:05:56","guid":{"rendered":"http:\/\/www.bitsworkshop.org\/wordpress\/?p=60"},"modified":"2023-05-15T09:59:51","modified_gmt":"2023-05-15T16:59:51","slug":"session-6-and-at-the-wafer-level","status":"publish","type":"post","link":"https:\/\/www.testconx.org\/premium\/2013\/session-6-and-at-the-wafer-level\/","title":{"rendered":"Session 6 – And, at the Wafer Level"},"content":{"rendered":"\n

Welcome!<\/span><\/h1>\n

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Session 6 – And, at the Wafer Level<\/h1>\n\nFor many in the industry, performing final test at the wafer level is still a novel idea. While providing some much needed solutions, it also comes with its own set of challenges. The four papers in this session look at wafer-level test from a number of different perspectives. The first one discusses the mechanical and electrical differences between wafer-level probe and wafer-level test using spring pins, focusing on requirements for performing final test at the wafer-level. The second presentation provides a comparison between traditional probe test for an RF wafer level chip scale package (WLCSP) and a final test socket solution. TSV issues lead our third author to share technologies that can bridge between 3D stacking and the 3D IC without TSVs. Finally, we\u2019ll gain insight into what some consider the holy grail of burn-in and test \u2013 wafer-level burn-in (WLBI). Now that WLBI is possible, it\u2019s important to understand when it\u2019s appropriate to consider WLBI versus other burn-in alternatives.
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\n\"Spring Probes and Probe Cards for Wafer-Level Test\"<\/strong>
\nJim Brandes
\nMultitest<\/p>\n

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\"PDF-Icon<\/a> Presentation Download<\/a>\t\t\t\t\t\t\t\t\t\t\t<\/p>\n

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\n\"A Comparison of Probe Solutions For an RF WLCSP Product\"<\/strong>
\nJames Migliaccio
\nRF Micro Devices<\/p>\n

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\"PDF-Icon<\/a> Presentation Download<\/a><\/p>\n

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\n\"Bridging Between 3D and 3D TSV Stacking Technologies\"<\/strong>
\nBelgacem Haba, Ph.D.
\nInvensas
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\"PDF-Icon<\/a> Presentation Download<\/a><\/p>\n

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\n\"Wafer-Level Burn-in Decision Factors\"<\/strong>
\nSteve Steps
\nAehr Test Systems<\/p>\n

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\"PDF-Icon<\/a> Presentation Download<\/a>\t\t\t\t\t\t\t\t\t\t\t<\/p>\n

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\nReturn to the 2013 BiTS Workshop Archive index page<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

For many in the industry, performing final test at the wafer level is still a novel idea. While providing some much needed solutions, it also comes with its own set of challenges. The four papers in this session look at wafer-level test from a number of different perspectives. The first one discusses the mechanical and electrical differences between wafer-level probe … <\/p>\n

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