{"id":56,"date":"2013-03-04T12:50:49","date_gmt":"2013-03-04T20:50:49","guid":{"rendered":"http:\/\/www.bitsworkshop.org\/wordpress\/?p=56"},"modified":"2023-05-15T09:59:51","modified_gmt":"2023-05-15T16:59:51","slug":"session-1-streamlining-operations","status":"publish","type":"post","link":"https:\/\/www.testconx.org\/premium\/2013\/session-1-streamlining-operations\/","title":{"rendered":"Session 1 – Streamlining Operations"},"content":{"rendered":"\n

Welcome!<\/span><\/h1>\n

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Session 1 – Streamlining Operations<\/h1>\n\nTest operations, generally considered costly yet necessary, add value to device manufacturing when optimized for efficiency. This session offers a variety of approaches that promise high yields, lean manufacturing, maximized performance at minimal costs, and optimized production times. The first paper discusses a method of incorporating multidimensional Monte Carlo analysis simulation with known design parameters to focus manufacturing improvement efforts and maximize alignment performance while minimizing costs. Presented next is a method for redefining test tooling design rules to gain process margin and prevent substrate chipping caused by test handler misalignment. Zero-cost, software based, virtual tool checkers that bring the whole production area towards a manufacturing LEAN direction is then discussed. Wrapping things up is a paper on a screwless socket and dual pin testing concept said to greatly enhance the robustness and efficiency of IC testing.
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\n\"Improving Socket Alignment Performance Using Monte Carlo Analysis Techniques and Manufacturing Controls\"<\/strong>
\nDaniel DelVecchio, Dustin Allison
\nInterconnect Devices Incorporated\t <\/p>\n

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\"PDF-Icon<\/a> Presentation Download<\/a>
\n\"Tooling Stack-up Process Margin Improvement\"<\/strong>
\nMook Koon Wong, Boon Hor Phee
\nIntel Malaysia\t <\/p>\n

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\"PDF-Icon<\/a> Presentation Download<\/a>
\n\"Zero Cost Virtual Tool Checker\"<\/strong>
\nSeong Guan Ooi
\nIntel Technology Sdn. Bhd.\t \t <\/p>\n

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\"PDF-Icon<\/a> Presentation Download<\/a>
\n\"Enablers for Robust & Online Trouble-shooting for High Parallelism Testing\"<\/strong>
\nBenedict Loh
\nInfineon Technologies\t<\/p>\n

Kohei Hironaka
\nNHK Springs\t<\/p>\n

Michelle Ng
\nTestPro<\/p>\n

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\"PDF-Icon<\/a> Presentation Download<\/a>\t\t\t\t\t<\/p>\n

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\nReturn to the 2013 BiTS Workshop Archive index page<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

Test operations, generally considered costly yet necessary, add value to device manufacturing when optimized for efficiency. This session offers a variety of approaches that promise high yields, lean manufacturing, maximized performance at minimal costs, and optimized production times. The first paper discusses a method of incorporating multidimensional Monte Carlo analysis simulation with known design parameters to focus manufacturing improvement efforts … <\/p>\n

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