
{"id":50,"date":"2013-03-05T12:10:53","date_gmt":"2013-03-05T20:10:53","guid":{"rendered":"http:\/\/www.bitsworkshop.org\/wordpress\/?p=50"},"modified":"2023-05-15T09:59:51","modified_gmt":"2023-05-15T16:59:51","slug":"session-4-bring-it-to-the-board-pcb-market-report","status":"publish","type":"post","link":"https:\/\/www.testconx.org\/premium\/2013\/session-4-bring-it-to-the-board-pcb-market-report\/","title":{"rendered":"Session 4 &#8211; Bring it to the Board (PCB) &#038; Market Report"},"content":{"rendered":"\n<h1><span style=\"color: #339966;\">Welcome!<\/span><\/h1>\n<h2>To access the archive contents (presentation slides, videos, multimedia, etc.) sign in using your LinkedIn account by clicking the LinkedIn button to the right. Full Conference Attendees and <a title=\"Access \u2013 Subscribe\" href=\"\/premium\/welcome\/\" title=\"Details about subscriptions\">Subscribers<\/a> have access to all content now. FREE guests, once signed in, have access to the presentations after June 1, 2013.<\/h2>\n<p><span style=\"color: #339966;\">------ This message is only displayed when you are not signed in. ------<\/span><\/p>\n<h1 class=\"entry-title\" style=\"font-weight:normal;\">Session 4 &#8211; Bring it to the Board (PCB) &#038; Market Report<\/h1>\n\nThe device under test (DUT) board is sometimes overlooked as a critical element in test-and burn-in strategies. This session brings PCBs into the limelight. The first presentation will cover some of the challenges that various DUT layouts present, demonstrating to semiconductor and ASICS design engineers the importance of considering final test hardware when designing device layouts. Another important consideration, covered in the second presentation, is the importance of performing RF characterization and simulation in-house to accurately measure the materials\u2019 electrical performance.<\/p>\n<p>As a bonus in this session, you\u2019ll get a look at the marketplace for test equipment and test consumables.<br \/>\n<!--more--><\/p>\n<p><strong>\"Building Optimized Test PCB\u2019s Starts at the DUT\"<\/strong><br \/>\nJoe Birtola<br \/>\nCMR Summit Technologies<\/p>\n<p><a href=\"\/premium\/welcome\/\"><img loading=\"lazy\" decoding=\"async\" class=\"alignleft size-full wp-image-129\" title=\"Click here to subscribe to PREMIUM content\" alt=\"\" src=\"\/premium\/wp-content\/uploads\/premium-video-non-subscriber.png\" width=\"480\" height=\"270\" srcset=\"https:\/\/www.testconx.org\/premium\/wp-content\/uploads\/premium-video-non-subscriber.png 480w, https:\/\/www.testconx.org\/premium\/wp-content\/uploads\/premium-video-non-subscriber-300x168.png 300w\" sizes=\"auto, (max-width: 480px) 100vw, 480px\" \/><\/a><\/p>\n<div style=\"clear: both;\"><\/div>\n<p><a href=\"\/premium\/wp-content\/uploads\/2013\/BiTS2013s4p1Birtola_3804.pdf\" target=\"_blank\"><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-70\" alt=\"PDF-Icon 150x139\" src=\"\/premium\/wp-content\/uploads\/PDF-Icon-150x139.png\" width=\"75\" height=\"70\" \/><\/a>&nbsp;<a href=\"\/premium\/wp-content\/uploads\/2013\/BiTS2013s4p1Birtola_3804.pdf\" target=\"_blank\" \/>Presentation Download<\/a>\t\t\t\t\t\t <\/p>\n<p><strong>\"High Frequency PCB Material Characterization and Simulation\"<\/strong><br \/>\nRyan Satrom<br \/>\nMultitest<\/p>\n<p><a href=\"\/premium\/welcome\/\"><img loading=\"lazy\" decoding=\"async\" class=\"alignleft size-full wp-image-129\" title=\"Click here to subscribe to PREMIUM content\" alt=\"\" src=\"\/premium\/wp-content\/uploads\/premium-video-non-subscriber.png\" width=\"480\" height=\"270\" srcset=\"https:\/\/www.testconx.org\/premium\/wp-content\/uploads\/premium-video-non-subscriber.png 480w, https:\/\/www.testconx.org\/premium\/wp-content\/uploads\/premium-video-non-subscriber-300x168.png 300w\" sizes=\"auto, (max-width: 480px) 100vw, 480px\" \/><\/a><\/p>\n<div style=\"clear: both;\"><\/div>\n<p><a href=\"\/premium\/wp-content\/uploads\/2013\/BiTS2013s4p2Satrom_6954.pdf\" target=\"_blank\"><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-70\" alt=\"PDF-Icon 150x139\" src=\"\/premium\/wp-content\/uploads\/PDF-Icon-150x139.png\" width=\"75\" height=\"70\" \/><\/a>&nbsp;<a href=\"\/premium\/wp-content\/uploads\/2013\/BiTS2013s4p2Satrom_6954.pdf\" target=\"_blank\" \/>Presentation Download<\/a>         <\/p>\n<h2>Market Report<\/h2>\n<p><strong>\"Market Trends in Test Equipment and Test Consumables\"<\/strong><br \/>\nJohn West<br \/>\nVLSI Research<\/p>\n<p><a href=\"\/premium\/welcome\/\"><img loading=\"lazy\" decoding=\"async\" class=\"alignleft size-full wp-image-129\" title=\"Click here to subscribe to PREMIUM content\" alt=\"\" src=\"\/premium\/wp-content\/uploads\/premium-video-non-subscriber.png\" width=\"480\" height=\"270\" srcset=\"https:\/\/www.testconx.org\/premium\/wp-content\/uploads\/premium-video-non-subscriber.png 480w, https:\/\/www.testconx.org\/premium\/wp-content\/uploads\/premium-video-non-subscriber-300x168.png 300w\" sizes=\"auto, (max-width: 480px) 100vw, 480px\" \/><\/a><\/p>\n<div style=\"clear: both;\"><\/div>\n<p><a href=\"\/premium\/wp-content\/uploads\/2013\/BiTS2013s4p3MarketReport-West_5067.pdf\" target=\"_blank\"><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-70\" alt=\"PDF-Icon 150x139\" src=\"\/premium\/wp-content\/uploads\/PDF-Icon-150x139.png\" width=\"75\" height=\"70\" \/><\/a>&nbsp;<a href=\"\/premium\/wp-content\/uploads\/2013\/BiTS2013s4p3MarketReport-West_5067.pdf\" target=\"_blank\" \/>Presentation Download<\/a>  \t\t\t\t\t<\/p>\n<p>&nbsp;<\/br><br \/>\nReturn to the 2013 BiTS Workshop Archive <a title=\"Return to 2013 Index\" href=\"\/premium\/bits-workshop-2013-event-archive\">index page<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>The device under test (DUT) board is sometimes overlooked as a critical element in test-and burn-in strategies. This session brings PCBs into the limelight. The first presentation will cover some of the challenges that various DUT layouts present, demonstrating to semiconductor and ASICS design engineers the importance of considering final test hardware when designing device layouts. Another important consideration, covered &#8230; <\/p>\n<div><a href=\"https:\/\/www.testconx.org\/premium\/2013\/session-4-bring-it-to-the-board-pcb-market-report\/\" class=\"more-link\">Read More<\/a><\/div>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[3],"tags":[],"class_list":["post-50","post","type-post","status-publish","format-standard","hentry","category-bits2013","no-post-thumbnail"],"_links":{"self":[{"href":"https:\/\/www.testconx.org\/premium\/wp-json\/wp\/v2\/posts\/50","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.testconx.org\/premium\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.testconx.org\/premium\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.testconx.org\/premium\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.testconx.org\/premium\/wp-json\/wp\/v2\/comments?post=50"}],"version-history":[{"count":16,"href":"https:\/\/www.testconx.org\/premium\/wp-json\/wp\/v2\/posts\/50\/revisions"}],"predecessor-version":[{"id":2621,"href":"https:\/\/www.testconx.org\/premium\/wp-json\/wp\/v2\/posts\/50\/revisions\/2621"}],"wp:attachment":[{"href":"https:\/\/www.testconx.org\/premium\/wp-json\/wp\/v2\/media?parent=50"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.testconx.org\/premium\/wp-json\/wp\/v2\/categories?post=50"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.testconx.org\/premium\/wp-json\/wp\/v2\/tags?post=50"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}