{"id":9090,"date":"2026-08-19T18:13:25","date_gmt":"2026-08-20T01:13:25","guid":{"rendered":"https:\/\/www.testconx.org\/premium\/?page_id=9090"},"modified":"2026-08-19T18:13:25","modified_gmt":"2026-08-20T01:13:25","slug":"testconx-korea-2026","status":"publish","type":"page","link":"https:\/\/www.testconx.org\/premium\/testconx-korea-2026\/","title":{"rendered":"TestConX Korea 2026"},"content":{"rendered":"
\"Image\"<\/span>

Suwon, South Korea - October 27, 2026<\/h1>\n<\/div><\/div><\/div>

SINTEX Convention Center<\/a><\/div>\n
(At LA VIE D'OR Resort)<\/a><\/div>\n
141-36 Botong-ri, Jeongnam-myeon, Hwaseong-si,<\/div>\n
Gyeonggi-do, South Korea<\/div><\/h1>\n<\/div><\/div><\/div><\/div><\/div><\/div><\/div>

TestConX<\/span><\/a>, over the course of its twenty-seven-year history, has established itself as the preeminent event for test consumables, test cell integration, and test operations. The program scope includes packaged semiconductor “final” test, burn-in, system level test, and beyond to encompass all practical aspects of electronics testing such as validation, advanced packaging testing, module test, and finished product test. <\/span><\/p>\n

Please join us for our 4th annual TestConX Korea! Don’t miss this opportunity to be part of TestConX as we connect a larger community of test professionals and to participate in this excellent event!<\/span><\/p>\n

 <\/p><\/div>

<\/div><\/div><\/div>

Tuesday October 27, 2026<\/h1>\n<\/div><\/div><\/div>

9:00<\/h1>\n<\/div><\/div><\/div><\/div>
\n
\n
Welcome<\/div><\/div>
<\/div>
<\/div>

<\/p><\/div>

\n
\n“Opening Remarks” \n<\/div>\n
\n
\n
\nIra Feldman\n <\/div>\n\t
\nFeldman Engineering\n\t <\/div>\n <\/div>\n<\/div>\n<\/div>\n<\/div>\n\t \n<\/div><\/div><\/div>

9:15<\/h1>\n<\/div><\/div><\/div><\/div>
\n
\n
Technical 1<\/div><\/div>
<\/div>
<\/div>

<\/p><\/div>

\n
\n“Electrical Performance Comparison between Coaxial and non-coaxial Elastomer Test Socket” \n
“\ub3d9\ucd95\/\ube44\ub3d9\ucd95 \uad6c\uc870\uc758 \uc5d8\ub77c\uc2a4\ud1a0\uba38 \ud14c\uc2a4\ud2b8 \uc18c\ucf13\uc758 \uc131\ub2a5 \ube44\uad50” \n<\/div>\n
\n
\n
\nJunyong Park\n <\/div>\n\t
\nKyung Hee University\n\t <\/div>\n <\/div>\n
\n
\nJimin \"JIMIN\" Song\n <\/div>\n\t
\nDankook University\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract - Biography (English)<\/summary>\n

High-speed semiconductor testing increasingly requires test sockets with improved signal integrity and electrical performance.
\nThis study compares the electrical characteristics of coaxial and non-coaxial elastomer test socket structures for high-speed test applications.
\nThe coaxial structure provides a controlled signal and ground configuration, enabling improved impedance control and reduced electromagnetic coupling between adjacent signal paths.
\nElectrical performance is evaluated in terms of insertion loss, return loss, crosstalk, and impedance characteristics over a wide frequency range.
\nThe results demonstrate the impact of socket interconnect architecture on high-frequency signal transmission and identify the performance advantages and design considerations of the coaxial configuration.
\nThese findings provide practical guidance for test socket design targeting next-generation high-speed and high-frequency semiconductor devices.<\/p><\/p>

Jimin Song is currently pursuing the M.S. degree in Semiconductor Engineering at Kyung Hee University, South Korea. His research focuses on electrical validation and signal integrity analysis of high-speed chiplet interconnects and advanced semiconductor packages.<\/p><\/p><\/details>\n

\n\t\ucd08\ub85d - \uc804\uae30 (Korean)<\/summary>\n

\uace0\uc18d \ubc18\ub3c4\uccb4 \ud14c\uc2a4\ud2b8 \ud658\uacbd\uc5d0\uc11c\ub294 \uc6b0\uc218\ud55c \uc2e0\ud638 \ubb34\uacb0\uc131(Signal Integrity)\uacfc \uc804\uae30\uc801 \ud2b9\uc131\uc744 \uac16\ub294 \ud14c\uc2a4\ud2b8 \uc18c\ucf13\uc758 \uc911\uc694\uc131\uc774 \uc810\ucc28 \uc99d\uac00\ud558\uace0 \uc788\ub2e4.
\n\ubcf8 \uc5f0\uad6c\uc5d0\uc11c\ub294 \uace0\uc18d \ud14c\uc2a4\ud2b8 \uc751\uc6a9\uc744 \uc704\ud55c \ub3d9\ucd95(Coaxial) \ubc0f \ube44\ub3d9\ucd95(Non-coaxial) \uc5d8\ub77c\uc2a4\ud1a0\uba38 \ud14c\uc2a4\ud2b8 \uc18c\ucf13 \uad6c\uc870\uc758 \uc804\uae30\uc801 \ud2b9\uc131\uc744 \ube44\uad50 \ubd84\uc11d\ud558\uc600\ub2e4.
\n\ub3d9\ucd95 \uad6c\uc870\ub294 \uc2e0\ud638\uc120\uacfc \uc811\uc9c0\uc758 \ubc30\uce58\ub97c \uc81c\uc5b4\ud568\uc73c\ub85c\uc368 \uc548\uc815\uc801\uc778 \uc784\ud53c\ub358\uc2a4 \ud2b9\uc131\uc744 \uad6c\ud604\ud558\uace0 \uc778\uc811 \uc2e0\ud638 \uac04 \uc804\uc790\uae30\uc801 \uacb0\ud569\uc744 \uac10\uc18c\uc2dc\ud0ac \uc218 \uc788\ub2e4.
\n\ub450 \uad6c\uc870\uc758 \uc804\uae30\uc801 \uc131\ub2a5\uc744 \uc0bd\uc785\uc190\uc2e4(Insertion Loss), \ubc18\uc0ac\uc190\uc2e4(Return Loss), \ub204\ud654(Crosstalk) \ubc0f \uc784\ud53c\ub358\uc2a4 \ud2b9\uc131\uc744 \uc911\uc2ec\uc73c\ub85c \uad11\ub300\uc5ed \uc8fc\ud30c\uc218 \uc601\uc5ed\uc5d0\uc11c \ud3c9\uac00\ud558\uc600\ub2e4.
\n\uc774\ub97c \ud1b5\ud574 \ud14c\uc2a4\ud2b8 \uc18c\ucf13\uc758 \uc778\ud130\ucee4\ub125\ud2b8 \uad6c\uc870\uac00 \uace0\uc8fc\ud30c \uc2e0\ud638 \uc804\uc1a1 \ud2b9\uc131\uc5d0 \ubbf8\uce58\ub294 \uc601\ud5a5\uc744 \ubd84\uc11d\ud558\uace0, \ub3d9\ucd95 \uad6c\uc870\uac00 \uc81c\uacf5\ud558\ub294 \uc804\uae30\uc801 \uc131\ub2a5\uc0c1\uc758 \uc774\uc810\uacfc \uc8fc\uc694 \uc124\uacc4 \uace0\ub824\uc0ac\ud56d\uc744 \uc81c\uc2dc\ud558\uc600\ub2e4.
\n\ubcf8 \uc5f0\uad6c \uacb0\uacfc\ub294 \ucc28\uc138\ub300 \uace0\uc18d\u00b7\uace0\uc8fc\ud30c \ubc18\ub3c4\uccb4 \ud14c\uc2a4\ud2b8\ub97c \uc704\ud55c \uc5d8\ub77c\uc2a4\ud1a0\uba38 \ud14c\uc2a4\ud2b8 \uc18c\ucf13 \uc124\uacc4 \ubc0f \ucd5c\uc801\ud654\uc5d0 \uc2e4\uc9c8\uc801\uc778 \uac00\uc774\ub4dc\ub77c\uc778\uc744 \uc81c\uacf5\ud560 \uc218 \uc788\ub2e4.<\/p><\/p>

\ubcf8 \ubc1c\ud45c\uc790 \uc1a1\uc9c0\ubbfc \ud559\uc0dd\uc740 \ud604\uc7ac \uacbd\ud76c\ub300\ud559\uad50 \ubc18\ub3c4\uccb4\uacf5\ud559\uacfc \uc11d\uc0ac\uacfc\uc815\uc5d0 \uc7ac\ud559 \uc911\uc774\ub2e4. \uc8fc\uc694 \uc5f0\uad6c \ubd84\uc57c\ub294 \uace0\uc18d Chiplet Interconnect\uc640 \ucca8\ub2e8 \ubc18\ub3c4\uccb4 \ud328\ud0a4\uc9c0\uc758 \uc804\uae30\uc801 \uac80\uc99d \ubc0f Signal Integrity \ubd84\uc11d\uc774\ub2e4.<\/p><\/p><\/details>\n<\/div>\n

\n
\n“Design optimization of Lightweight Metal Trays in High-Temperature Reflow Processes of Advanced HBM Packages” \n<\/div>\n
\n
\n
\nGyuyeol Kim\n <\/div>\n\t
\nSamsung Electronics\n\t <\/div>\n <\/div>\n
\n
\nJaewoong Choi\n <\/div>\n\t
\nSamsung\n\t <\/div>\n <\/div>\n
\n
\nHyunjae Lee\n <\/div>\n\t
\nSamsung\n\t <\/div>\n <\/div>\n
\n
\nInjae Lee\n <\/div>\n\t
\nsamsung\n\t <\/div>\n <\/div>\n
\n
\nWonhong Choi\n <\/div>\n\t
\nSamsung\n\t <\/div>\n <\/div>\n
\n
\nJeongHwan Kim\n <\/div>\n\t
\nSamsung\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract - Biography (English)<\/summary>\n

As large packages such as HBM see wider adoption, the metal trays used in high-temperature reflow processes for reliability testing can cause thermal damage to transfer components, such as the equipment's internal conveyor belts, creating a need for tray temperature-reduction design technology. This study proposes an optimal design that reduces the tray's heat capacity through lightweight design, thereby lowering the post-reflow tray temperature. The approach is developed and validated through finite element analysis (FEA) and prototype evaluation.<\/p>\n<\/p>

Gyu-Yeol Kim received his B.S. degree in Electrical Engineering from Kyunghee University, Suwon, Korea, in 2000, and his M.S. and Ph.D. degrees in Electrical Engineering from Sungkyunkwan University, Suwon, Korea, in 2008 and 2017, respectively. His current research interests include the design of memory package boards, sockets, and probe cards. Since 2000, he has been with Samsung Electronics, where he is a Principal Engineer of the EDS Test Technology Group.<\/p>\n<\/p><\/details>\n

\n\t\u6458\u8981 (Chinese)<\/summary>\n

\uc2e0\ub8b0\uc131 \uac80\uc99d \uace0\uc628 \ub9ac\ud50c\ub85c\uc6b0 \uacf5\uc815\uc6a9 HBM \uba54\ud0c8 \ud2b8\ub808\uc774\uc758 \uacbd\ub7c9\ud654 \uc124\uacc4 \ucd5c\uc801\ud654<\/p>

<\/p><\/details>\n

\n\t\ucd08\ub85d - \uc804\uae30 (Korean)<\/summary>\n

HBM\uacfc \uac19\uc740 \ub300\ud615 \ud328\ud0a4\uc9c0\uc758 \uc801\uc6a9 \ud655\ub300\uc5d0 \ub530\ub77c \uc2e0\ub8b0\uc131 \ud3c9\uac00\ub97c \uc704\ud55c \uace0\uc628 \ub9ac\ud50c\ub85c\uc6b0 \uacf5\uc815\uc5d0 \uc0ac\uc6a9\ub418\ub294 \uba54\ud0c8 \ud2b8\ub808\uc774\ub97c \uc774\uc6a9\ud55c \uc7a5\ube44 \ub0b4\ubd80 \ubc18\uc1a1 \ubca8\ud2b8 \ub4f1 \uc774\uc1a1 \ubd80\ud488\uc758 \uc5f4\uc190\uc0c1\uc744 \uc720\ubc1c\ud560 \uc218 \uc788\uc5b4 \ud2b8\ub808\uc774 \uc628\ub3c4 \uc800\uac10 \uc124\uacc4 \uae30\uc220\uc774 \uc694\uad6c\ub41c\ub2e4. \ubcf8 \uc5f0\uad6c\uc5d0\uc11c\ub294 \uba54\ud0c8 \ud2b8\ub808\uc774\uc758 \uacbd\ub7c9\ud654\ub97c \ud1b5\ud574 \uc5f4\uc6a9\ub7c9\uc744 \uac10\uc18c\uc2dc\ucf1c \ub9ac\ud50c\ub85c\uc6b0 \uc774\ud6c4 \ud2b8\ub808\uc774 \uc628\ub3c4\ub97c \ub0ae\ucd9c \uc218 \uc788\ub3c4\ub85d \uc720\ud55c\uc694\uc18c\ud574\uc11d\uacfc \uc2dc\uc81c\ud488 \ud3c9\uac00\ub97c \ud1b5\ud55c \ucd5c\uc801 \uc124\uacc4 \ubc29\uc548\uc744 \uc81c\uc548\ud55c\ub2e4.<\/p>\n<\/p>

\uacbd\ud76c\ub300\ud559\uad50 \uc804\uc790\uacf5\ud559\uacfc(2000), \uc131\uade0\uad00\ub300\ud559\uad50 \uc804\uae30\uc804\uc790\uacf5\ud559\uacfc \uc11d\uc0ac(2008), \ubc15\uc0ac(2017), 2000\ub144 2\uc6d4 ~ \ud604\uc7ac: \uc0bc\uc131\uc804\uc790(\uba54\ubaa8\ub9ac) \uc218\uc11d\uc5f0\uad6c\uc6d0. \uad00\uc2ec\ubd84\uc57c: package test board, socket, probe card, memory test.<\/p>\n<\/p><\/details>\n<\/div>\n<\/div>\n\t \n<\/div><\/div><\/div>

10:15<\/h1>\n<\/div><\/div><\/div><\/div>

Break & Networking<\/strong><\/h1>\nEnjoy time to meet with the presenters and network while refreshments are served.<\/span><\/span><\/div><\/div><\/div>
<\/div><\/div><\/div>

10:45<\/h1>\n<\/div><\/div><\/div><\/div>
\n
\n
Keynote<\/div><\/div>
<\/div>
<\/div>

<\/p><\/div><\/div>\n\t \n

\"Prof.<\/span><\/div>

Prof. Donghwan Ahn<\/strong> is presently a professor in the School of Materials Science and Engineering at Kookmin University, Seoul, Korea. Prior to joining Kookmin University, he was a Senior Research Engineer and a team leader of Advanced Silicon Photonics and Electronics Lab at Samsung Electronics U.S. R&D Center (SAIT-USA). He received B.S. and M.S. degrees in materials science and engineering from Seoul National University, South Korea, in 1996 and 2000, respectively.<\/p><\/div><\/div><\/div><\/div>

He earned his Ph.D. degree from Massachusetts Institute of Technology (MIT) in 2007, under the guidance of Prof. Lionel C. Kimerling. In his Ph.D. dissertation entitled “Intra-chip Clock Signal Distribution via Si-based Optical Interconnect”, he pioneered an H-tree waveguide network and demonstrated the world’s first waveguide-integrated germanium photodetector, which is now widely adopted in optical engine chiplets for Co-Package Optics (CPO). Prior to joining Samsung, he was an NSF\/ASEE Research Fellow at Bell Laboratories, Alcatel-Lucent, where he conducted research on silicon CMOS-compatible photonic devices in the Advanced Photonic Integration group, and a Senior Research Scientist at Astrowatt Inc., a solar cell start-up company in Austin, Texas. His current research interests include germanium-based photonic and electronic devices, optical interconnect and packaging for AI and high-performance computing, and photonic integrated circuits for quantum computing chip.<\/p><\/div><\/div><\/div><\/div>

<\/div><\/div><\/div>

11:45<\/h1>\n<\/div><\/div><\/div><\/div>

Lunch & EXPO<\/strong><\/h1>\nEnjoy the delicious hot buffet lunch and networking time. Then take the time to explore the TestConX EXPO. There will be many great exhibits to connect electronic test professionals to solutions. You will be certain to see something new or meet someone new. As attendees to TestConX know, there is always excellent food, drinks, and time for attendees to network with exhibitors! TestConX EXPO will open at 11:45 and will remain open throughout the afternoon until 18:00
<\/span><\/span><\/div><\/div><\/div>
<\/div><\/div><\/div>

13:30<\/h1>\n<\/div><\/div><\/div><\/div><\/div><\/div>
<\/div>
\n
\n
Distinguished<\/div><\/div>
<\/div>
<\/div>

<\/p><\/div><\/div>\n\t \n

\"Image\"<\/span><\/div>

\uac00\uc82f\uc11c\uc6b8 \ubbf8\ub514\uc5b4\uc758 \uc7a5\uc9c0\ud6c8 \ub300\ud45c\ub294 \ud55c\uad6d\uc678\uad6d\uc5b4\ub300\ud559\uad50\ub97c \uc878\uc5c5\ud55c \ud6c4 \ud55c\ud654\uadf8\ub8f9 \uacf5\ucc44\ub85c \ucee4\ub9ac\uc5b4\ub97c \uc2dc\uc791\ud588\ub2e4. \uc804\ub7b5\/\uae30\ud68d\ud300\uc5d0\uc11c \uadfc\ubb34\ud558\uba70 IT \ubd84\uc57c\uc758 \uba38\ucc9c\ub2e4\uc774\uc800\ub85c \ube0c\ub79c\ub4dc\uc640 \uc0c1\ud488\uc744 \uc804\uac1c\ud558\uc600\ub2e4. \uc774\ud6c4 \uacbd\uc81c\uc9c0 \uc774\ucf54\ub178\ubbf8 \uc870\uc120\uc758 IT\uc804\ubb38 \uce7c\ub7fc\ub2c8\uc2a4\ud2b8\ub85c \uc5c5\uacc4\uc758 \uc2dc\ud669\uacfc \uc120\ud589\uae30\uc220\ub4e4\uc5d0 \ub300\ud55c \uae4a\uc774 \uc788\ub294 \uc778\uc0ac\uc774\ud2b8\ub97c \uacf5\uc720\ud574\uc654\ub2e4. \ud604\uc7ac\ub294 \uc720\ud29c\ube0c \ucc44\ub110 \uac00\uc82f\uc11c\uc6b8\uc744 \ud1b5\ud574 \uc0c1\ud488\uacfc \ube0c\ub79c\ub4dc, \uae30\uc220\uacfc \uc2dc\ud669\uc744 \uade0\ud615\uac10\uc788\uac8c \uc870\ub9dd\ud558\ub294 \uc601\uc0c1 \uce7c\ub7fc\uc744 \uc81c\uacf5\ud558\uace0 \uc788\ub2e4.<\/p><\/div><\/div><\/div><\/div>

Jihoon Jang, the CEO of Gadgetseoul Media, developed and narrates the highly informative and popular Gadgetseoul YouTube channel<\/a> focused on semiconductors and technology. Prior to which he was an Information Technology columnist for Economy<\/i> Chosun<\/i>. He started his career at Hanwha group as an IT\/Tech Merchandiser, managing and promoting many brands and products on the Strategy\/Planning team after completing his studies at Hankuk University of Foreign Studies.<\/p><\/div>

\n
\n
Market<\/div><\/div>
<\/div>
<\/div>

<\/p><\/div>

\n
\n“How high-performance packaging is reshaping the test and burn-in socket market.” \n<\/div>\n
\n
\n
\nJohn West\n <\/div>\n\t
\nYole Group\n\t <\/div>\n <\/div>\n<\/div>\n<\/div>\n<\/div>\n\t \n<\/div><\/div><\/div>

14:45<\/h1>\n<\/div><\/div><\/div><\/div>

Posters & EXPO<\/strong><\/h1>\nEnjoy time to meet with the presenters and network while refreshments are served.<\/span><\/span><\/div><\/div><\/div>
\n
\n
Posters<\/div><\/div>
<\/div>
<\/div>

<\/p><\/div>

\n
\n“Improving Productivity in Test Program Management with GitHub Version Control” \n<\/div>\n
\n
\n
\nAnastasiia Makhniaieva\n <\/div>\n\t
\nElevATE Semiconductor\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract (English)<\/summary>\n

Managing Automated Test Equipment (ATE) test programs using traditional methods like shared drives created significant challenges for our team. It was often difficult to track changes across multiple files and versions, leading to confusion and potential errors. Coordinating parallel development tasks was complicated, especially when working with distributed teams and external vendors responsible for creating and debugging test programs. These issues frequently caused communication breakdowns, inefficient workflows, prolonged debugging cycles, and delayed product releases.<\/p>\n\n

To tackle these challenges, we transitioned our version control process to GitHub, adopting a structured workflow with branches and tagged releases. GitHub, widely recognized and commonly used in software development, gave us a transparent and straightforward approach to organizing and managing test program versions. We developed consistent branching strategies aligned with our development phases and regularly used tags to indicate stable releases and important milestones. This allowed us to manage multiple concurrent test code versions effectively.<\/p>\n\n

By streamlining our communication through clearly documented commits and leveraging GitHub\u2019s collaborative tools, we reduced the need for frequent coordination meetings with external vendors. This significantly enhanced our efficiency, resulting in development timelines improving by up to 40%.<\/p>\n\n

Since moving to GitHub, we\u2019ve experienced notable productivity improvements. It has become significantly easier to handle multiple projects simultaneously and maintain accurate and detailed records of changes. Debugging and validation processes have become faster due to enhanced visibility into code changes, allowing us to quickly pinpoint and resolve issues. Our release processes have also become more reliable, with preparation times reduced from several days to just a few hours.<\/p>\n\n

One of the greatest advantages has been the improvement in collaboration, both within our internal engineering teams and with external vendor partners. Everyone now benefits from clear visibility into ongoing development activities and quick access to the latest test program versions. This improved communication helps us rapidly adapt to design modifications, customer feedback, and changing testing requirements, which is critical in today\u2019s dynamic semiconductor environment. Additionally, using GitHub as our collaboration platform enabled seamless, around-the-clock development in partnership with international teams. By exchanging and updating ASCII files directly on GitHub, we eliminated delays from downloading or transferring files, significantly speeding up our joint workflow.<\/p>\n\n

Overall, integrating GitHub into our ATE test program management has greatly improved our workflow efficiency, strengthened collaboration, enhanced traceability, and significantly boosted productivity. This strategic shift has streamlined our current operations and better positioned us to support future advancements in semiconductor test engineering.<\/p><\/p>

<\/p><\/details>\n<\/div>\n

\n
\n“Testing the 20 bit Digital to Analog Converter using a Bench top rack and stack system” \n<\/div>\n
\n
\n
\nRajesh Sur\n <\/div>\n\t
\nElevate\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract (English)<\/summary>\n

Testing of 20-bit digital-to-analog converters (DACs) is typically performed using automated test equipment, which is costly and requires complex handler configuration. As an alternative, the rack-and-stack method facilitates testing without such expensive equipment by employing a digital pattern generator to supply the required digital codes. Comprehensive evaluation of a 20-bit DAC necessitates 1,048,576 digital codes. Although this method increases test duration and reduces product margin, this study presents a methodology utilizing a desktop rack-and-stack system to generate digital patterns, apply them to a 20-bit DAC, and measure the resulting output voltage.<\/p>\n\n

The output voltage is measured with an integrated oscilloscope, and a Python script is implemented to assess differential nonlinearity (DNL), integral nonlinearity (INL), offset error, and gain error. The same rack-and-stack benchtop system is used to describe the methodology for measuring power supply rejection ratio (PSRR). The measurement system includes a network analyzer capable of sweeping the ripple frequency in under thirty minutes and generating a PSRR report. Software algorithms for PSRR measurement are detailed, and the assessment of AC characteristics of a 20-bit DAC using the rack-and-stack test system is also addressed.<\/p>\n\n

The methodology to reduce ripple caused by di\/dt during power system activation is discussed. Additionally, the use of a Faraday cage is examined to minimize radio frequency interference during the measurement of DC and AC parameters of digital-to-analog converters.<\/p><\/p>

<\/p><\/details>\n<\/div>\n

\n
\n“Precision DAC converter testing” \n<\/div>\n
\n
\n
\nRajesh Sur\n <\/div>\n\t
\nElevate\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract (English)<\/summary>\n

Accurate testing of 12-, 16-, and 20-bit Digital-to-Analog Converters requires a precision voltage supply to measure differential non-linearity, integral non-linearity, gain error, and offset error. This paper details the delivery of precise on-board analog, digital, and reference voltages using a highly efficient 95% buck-boost converter.<\/p>\n\n

The described DC-DC converter features an enable pin for power sequencing, which can be controlled via a switch or a microcontroller's general-purpose input\/output (GPIO) pin. Minor voltage drops may result from the board's inherent IR drop. The methodology uses an 8-bit Digital-to-Analog Converter (DAC) in the feedback path to ensure precise voltage delivery to the device under test. In contrast to conventional DC-DC converters that rely on feedback resistors, integrating an 8-bit DAC simplifies voltage control.<\/p>\n\n

Further technical details are presented in subsequent sections. Within the graphical user interface (GUI), the 8-bit DAC control bit should be set before applying a precise voltage to the integrated circuit pins. The DC-DC converter can deliver up to 3.87 V at 5 A and support up to 15 converters on a single test board, offering a cost-effective solution.<\/p><\/p>

<\/p><\/details>\n<\/div>\n<\/div>\n\t \n

<\/div><\/div><\/div>

15:45<\/h1>\n<\/div><\/div><\/div><\/div>
\n
\n
Technical 2<\/div><\/div>
<\/div>
<\/div>

<\/p><\/div>

\n
\n“Diagnosing SOA-Induced Aging Drift in Analog Pin Electronics: Implications for AI and HPC Test” \n
“\u8bca\u65ad\u6a21\u62df\u5f15\u811a\u7535\u5b50\u5668\u4ef6\u4e2d\u7531SOA\u5f15\u8d77\u7684\u8001\u5316\u6f02\u79fb\uff1a\u5bf9AI\u4e0eHPC\u6d4b\u8bd5\u7684\u542f\u793a” \n<\/div>\n
\n
\n
\nHailin Wang\n <\/div>\n\t
\nElevATE Semiconductor\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract - Biography (English)<\/summary>\n

\nSilent Data Corruption (SDC)<\/strong> and post-deployment hardware faults have emerged as significant reliability concerns for hyperscale AI and HPC infrastructure, with recent industry reports from Google, Meta, and the Open Compute Project (OCP) highlighting defects that pass manufacturing test but only manifest under specific bias conditions or after extended operation. The published case studies are predominantly digital. In this study, we examine the same failure class in an analog Automated Test Equipment (ATE)<\/strong> pin electronics ASIC, devices that perform final test on AI and HPC silicon.\n<\/p>\n\n

\nA customer reported progressive VCOM threshold drift<\/strong> on a 256-channel application, affecting approximately 50%<\/strong> of channels and continuing past -900 mV<\/strong> with no observable stabilization. All affected devices had passed final test before production. Failing devices were inspected, and results from initial visual inspection, ATE re-test, and emission microscopy were inconclusive. Bench characterization across 50 devices<\/strong> spanning multiple lots and date codes confirmed that the drift was reproducible and exhibited strong dependence on register configuration and operating temperature but evaded standard production screening due to its time-dependent nature.\n<\/p>\n\n

\nFailure analysis techniques such as Focused Ion Beam (FIB)<\/strong> produced misleading initial results. Severing a capacitor and diode in the comparator path arrested the drift, which initially appeared to identify the offending components. A subsequent control FIB cutting non-functional metal also halted the drift, demonstrating that the FIB process itself was perturbing the measurement rather than the targeted devices. This sensitivity to invasive characterization is a notable hazard for this defect class and constrains the design of subsequent debug experiments.\n<\/p>\n\n

\nRoot cause was traced to Safe Operating Area (SOA)<\/strong> violations within the analog comparator. Floating-node conditions in one register state and an over-stressed gain-stage VGS<\/sub><\/strong> in another subjected gate oxides to chronic overstress, accelerating Hot Carrier Injection (HCI)<\/strong> and Bias Temperature Instability (BTI)<\/strong>. Pre-silicon simulation did not flag the floating-node case due to the initial conditions the simulator applies, preventing the very condition responsible. Final test could not screen for the effect because the resulting offset is sub-microvolt at t = 0<\/strong> and accumulates only after days of biased operation.\n<\/p>\n\n

\nThis case study underscores the importance of integrating aging-aware design verification with adaptive test strategies for analog devices intended for long-deployment applications. The presentation walks through the diagnostic flow, the validated workaround shipped to the customer during silicon respin development, and the design corrections incorporated in successor revisions. We conclude with recommendations for screening long-latency, bias-dependent drift in the analog devices on which AI and HPC test programs increasingly depend, including SOA analysis<\/strong> during pre-silicon verification, extended-stress characterization protocols<\/strong>, and closer coordination between design verification and production test engineering teams.\n<\/p><\/p>

Hailin is an Applications Engineer at ElevATE Semiconductor with a strong engineering background and a passion for innovation. He holds a degree from the University of Toronto, where he also engaged in academic research collaborations, and has professional experience spanning software development and mixed-signal engineering.<\/p>\n\n

Dedicated to tackling complex technical challenges and fostering opportunities for students, Hailin is committed to advancing the field of semiconductor test while inspiring the next generation of professionals. He is currently pursuing a master\u2019s degree at UC Berkeley, focusing on applying statistical models and data science principles to enhance test engineering.<\/p><\/p><\/details>\n

\n\t\u6458\u8981 - \u7b80\u4ecb (Chinese)<\/summary>\n

\u9759\u9ed8\u6570\u636e\u635f\u574f\uff08SDC\uff09\u4e0e\u90e8\u7f72\u540e\u786c\u4ef6\u6545\u969c\u5df2\u6210\u4e3a\u8d85\u5927\u89c4\u6a21AI\u4e0eHPC\u57fa\u7840\u8bbe\u65bd\u53ef\u9760\u6027\u7684\u91cd\u8981\u8bae\u9898\uff0cGoogle\u3001Meta\u53ca\u5f00\u653e\u8ba1\u7b97\u9879\u76ee\uff08OCP\uff09\u8fd1\u671f\u62a5\u544a\u5747\u6307\u51fa\uff0c\u90e8\u5206\u7f3a\u9677\u5668\u4ef6\u53ef\u901a\u8fc7\u51fa\u5382\u6d4b\u8bd5\uff0c\u5374\u4ec5\u5728\u7279\u5b9a\u504f\u7f6e\u6761\u4ef6\u6216\u957f\u671f\u8fd0\u884c\u540e\u624d\u4f1a\u663e\u73b0\u3002\u5df2\u53d1\u8868\u6848\u4f8b\u4ee5\u6570\u5b57\u5668\u4ef6\u4e3a\u4e3b\uff0c\u672c\u7814\u7a76\u5219\u9488\u5bf9\u540c\u7c7b\u6545\u969c\u673a\u5236\u5728\u6a21\u62df\u81ea\u52a8\u6d4b\u8bd5\u8bbe\u5907\uff08ATE\uff09\u5f15\u811a\u7535\u5b50\u4e13\u7528\u96c6\u6210\u7535\u8def\uff08ASIC\uff09\u4e2d\u7684\u8868\u73b0\u8fdb\u884c\u5206\u6790\u3002<\/p>\n\n

\u67d0\u5ba2\u6237\u62a5\u544a\u5728\u4e00\u6b3e256\u901a\u9053\u5e94\u7528\u4e2d\u51fa\u73b0\u6e10\u8fdb\u6027VCOM\u9608\u503c\u6f02\u79fb\uff0c\u7ea650%\u901a\u9053\u53d7\u5f71\u54cd\uff0c\u4e14\u65e0\u6536\u655b\u8ff9\u8c61\uff0c\u6240\u6709\u5668\u4ef6\u5747\u5df2\u901a\u8fc7\u51fa\u5382\u6d4b\u8bd5\u3002\u521d\u6b65\u76ee\u89c6\u68c0\u67e5\u3001ATE\u590d\u6d4b\u53ca\u53d1\u5c04\u663e\u5fae\u955c\u68c0\u6d4b\u5747\u65e0\u6cd5\u5b9a\u4f4d\u95ee\u9898\u3002\u8de8\u6279\u6b21\u53f0\u67b6\u8868\u5f81\u8bc1\u5b9e\u8be5\u6f02\u79fb\u53ef\u91cd\u590d\uff0c\u4e14\u4e0e\u5bc4\u5b58\u5668\u914d\u7f6e\u53ca\u5de5\u4f5c\u6e29\u5ea6\u5bc6\u5207\u76f8\u5173\uff0c\u56e0\u5176\u65f6\u95f4\u4f9d\u8d56\u7279\u6027\u800c\u672a\u88ab\u6807\u51c6\u91cf\u4ea7\u7b5b\u9009\u6355\u83b7\u3002<\/p>\n\n

\u805a\u7126\u79bb\u5b50\u675f\uff08FIB\uff09\u5206\u6790\u521d\u671f\u7ed9\u51fa\u8bef\u5bfc\u6027\u7ed3\u679c\uff1a\u5207\u65ad\u6bd4\u8f83\u5668\u8def\u5f84\u4e2d\u7684\u7279\u5b9a\u5143\u4ef6\u540e\u6f02\u79fb\u5373\u505c\u6b62\uff0c\u4f46\u540e\u7eed\u5bf9\u7167\u5b9e\u9a8c\u663e\u793a\uff0c\u5207\u5272\u65e0\u529f\u80fd\u91d1\u5c5e\u8d70\u7ebf\u540c\u6837\u80fd\u4e2d\u6b62\u6f02\u79fb\uff0c\u8bc1\u660e\u662fFIB\u52a0\u5de5\u8fc7\u7a0b\u672c\u8eab\u5e72\u6270\u4e86\u6d4b\u91cf\u3002\u8fd9\u4e00\u73b0\u8c61\u63ed\u793a\u4e86\u8be5\u7c7b\u7f3a\u9677\u5bf9\u4fb5\u5165\u5f0f\u8868\u5f81\u624b\u6bb5\u7684\u654f\u611f\u6027\uff0c\u4e5f\u9650\u5236\u4e86\u540e\u7eed\u8c03\u8bd5\u5b9e\u9a8c\u7684\u8bbe\u8ba1\u3002<\/p>\n\n

\u6839\u672c\u539f\u56e0\u88ab\u8ffd\u6eaf\u81f3\u6a21\u62df\u6bd4\u8f83\u5668\u5185\u90e8\u7684\u5b89\u5168\u5de5\u4f5c\u533a\uff08SOA\uff09\u8fdd\u89c4\uff1a\u7279\u5b9a\u5bc4\u5b58\u5668\u72b6\u6001\u4e0b\u7684\u60ac\u7a7a\u8282\u70b9\u53ca\u589e\u76ca\u7ea7\u8fc7\u5e94\u529b\uff0c\u4f7f\u6805\u6c27\u5316\u5c42\u957f\u671f\u627f\u53d7\u8fc7\u5e94\u529b\uff0c\u52a0\u901f\u4e86\u70ed\u8f7d\u6d41\u5b50\u6ce8\u5165\uff08HCI\uff09\u4e0e\u504f\u7f6e\u6e29\u5ea6\u4e0d\u7a33\u5b9a\u6027\uff08BTI\uff09\u6548\u5e94\u3002\u7531\u4e8e\u4eff\u771f\u521d\u59cb\u6761\u4ef6\u89c4\u907f\u4e86\u60ac\u7a7a\u8282\u70b9\u72b6\u6001\uff0c\u524d\u7845\u4eff\u771f\u672a\u80fd\u6355\u6349\u8be5\u95ee\u9898\uff1b\u800c\u7531\u6b64\u4ea7\u751f\u7684\u504f\u79fb\u5728t=0\u65f6\u4ec5\u4e3a\u4e9a\u5fae\u4f0f\u7ea7\uff0c\u987b\u7ecf\u6570\u65e5\u504f\u7f6e\u8fd0\u884c\u65b9\u9010\u6e10\u663e\u73b0\uff0c\u56e0\u800c\u4e5f\u65e0\u6cd5\u88ab\u6700\u7ec8\u6d4b\u8bd5\u7b5b\u51fa\u3002<\/p>\n\n

\u672c\u6848\u4f8b\u7814\u7a76\u8868\u660e\uff0c\u9488\u5bf9\u957f\u671f\u90e8\u7f72\u5e94\u7528\u7684\u6a21\u62df\u5668\u4ef6\uff0c\u9700\u5c06\u8001\u5316\u611f\u77e5\u8bbe\u8ba1\u9a8c\u8bc1\u4e0e\u81ea\u9002\u5e94\u6d4b\u8bd5\u7b56\u7565\u76f8\u7ed3\u5408\u3002\u62a5\u544a\u5c06\u4ecb\u7ecd\u8bca\u65ad\u6d41\u7a0b\u3001\u63d0\u4f9b\u7ed9\u5ba2\u6237\u7684\u9a8c\u8bc1\u6027\u4e34\u65f6\u65b9\u6848\uff0c\u4ee5\u53ca\u540e\u7eed\u7248\u672c\u4e2d\u7684\u8bbe\u8ba1\u6539\u8fdb\uff0c\u5e76\u5c31\u524d\u7845SOA\u5206\u6790\u3001\u6269\u5c55\u5e94\u529b\u8868\u5f81\u53ca\u8bbe\u8ba1\u9a8c\u8bc1\u4e0e\u91cf\u4ea7\u6d4b\u8bd5\u56e2\u961f\u534f\u4f5c\u63d0\u51fa\u5efa\u8bae\uff0c\u4ee5\u7b5b\u67e5AI\u4e0eHPC\u6d4b\u8bd5\u6240\u4f9d\u8d56\u7684\u6a21\u62df\u5668\u4ef6\u4e2d\u957f\u6f5c\u4f0f\u671f\u3001\u504f\u7f6e\u4f9d\u8d56\u6027\u6f02\u79fb\u95ee\u9898\u3002<\/p><\/p>

Hailin \u662f ElevATE Semiconductor \u7684\u5e94\u7528\u5de5\u7a0b\u5e08\uff0c\u5177\u5907\u624e\u5b9e\u7684\u5de5\u7a0b\u80cc\u666f\u5e76\u5bf9\u521b\u65b0\u5145\u6ee1\u70ed\u60c5\u3002\u4ed6\u6bd5\u4e1a\u4e8e\u591a\u4f26\u591a\u5927\u5b66\uff0c\u5e76\u53c2\u4e0e\u4e86\u591a\u9879\u5b66\u672f\u7814\u7a76\u5408\u4f5c\uff0c\u804c\u4e1a\u7ecf\u5386\u6db5\u76d6\u8f6f\u4ef6\u5f00\u53d1\u4e0e\u6df7\u5408\u4fe1\u53f7\u5de5\u7a0b\u3002<\/p>\n\n

Hailin \u81f4\u529b\u4e8e\u89e3\u51b3\u590d\u6742\u7684\u6280\u672f\u6311\u6218\u5e76\u4e3a\u5b66\u751f\u521b\u9020\u673a\u4f1a\uff0c\u4e13\u6ce8\u4e8e\u63a8\u52a8\u534a\u5bfc\u4f53\u6d4b\u8bd5\u9886\u57df\u7684\u53d1\u5c55\uff0c\u540c\u65f6\u6fc0\u52b1\u4e0b\u4e00\u4ee3\u5de5\u7a0b\u4e13\u4e1a\u4eba\u624d\u3002\u4ed6\u76ee\u524d\u6b63\u5728\u52a0\u5dde\u5927\u5b66\u4f2f\u514b\u5229\u5206\u6821\u653b\u8bfb\u7855\u58eb\u5b66\u4f4d\uff0c\u7814\u7a76\u91cd\u70b9\u662f\u8fd0\u7528\u7edf\u8ba1\u6a21\u578b\u548c\u6570\u636e\u79d1\u5b66\u539f\u7406\u63d0\u5347\u6d4b\u8bd5\u5de5\u7a0b\u6c34\u5e73\u3002<\/p><\/p><\/details>\n<\/div>\n

\n
\n“From Test Floor to Thinking Floor: The Agentic Future of Silicon Test” \n
“\ud14c\uc2a4\ud2b8 \ud50c\ub85c\uc5b4\uc5d0\uc11c \uc53d\ud0b9 \ud50c\ub85c\uc5b4\ub85c: \ubc18\ub3c4\uccb4 \ud14c\uc2a4\ud2b8\uc758 \uc5d0\uc774\uc804\ud2b8 \uae30\ubc18 \ubbf8\ub798” \n<\/div>\n
\n
\n
\nMykola Zakharchuk\n <\/div>\n\t
\nAdvantest\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract - Biography (English)<\/summary>\n

Abstract<\/h3>\n\n

\nSemiconductor test today operates as a sequence of disconnected stages \u2014 EDA, wafer sort, final test,\nsystem-level test, reliability, and field \u2014 each with its own tools, its own datalog format, and its own engineering\nteams. The result is well understood across the industry: an SLT escape rarely traces cleanly back to a sort\nsignature, characterization data is reconstructed by hand for every yield investigation, and the engineer's most\nexpensive task is not running tests but stitching context together across stages.\n<\/p>\n\n

\nThis talk proposes a different shape for the next decade of test: a thinking test floor in which the tester becomes\na deterministic execution engine, the IDE becomes optional, and a fleet of discipline-specialized AI agents \u2014\nTest, Thermal, Characterization, Yield, Reliability, SLT, Application Engineering \u2014 operates above a unified\nanalytics platform on a common Device Log that follows each die from EDA through field return.\n<\/p>\n\n

\nWe will outline a vendor-neutral, three-layer architecture that makes this possible:\n<\/p>\n\n

    \n
  1. \n An Agent Fleet<\/strong> the engineer steers at the level of intent rather than clicks.\n <\/li>\n
  2. \n An Agentic Control Plane<\/strong> that translates intent into measurement operations through\n domain-shaped tools and enforces hardware-safety envelopes structurally.\n <\/li>\n
  3. \n A headless execution layer<\/strong> with a stable contract for ingesting machine-authored,\n signed, version-controlled test programs.\n <\/li>\n<\/ol>\n\n

    \nBinding the three layers together is a Unified Device Log<\/strong> \u2014 a schemaed, append-only,\ncustomer-owned record keyed to each device's lifelong identity \u2014 which turns cross-stage investigation from a\nproject into a query.\n<\/p>\n\n

    \nWe will also examine the corresponding shift toward simulation-led test development, in which agents iterate\nagainst virtual testers and digital-twin device models long before silicon is touched, and discuss what this means\nfor tooling, IP boundaries, customer trust, and the engineering organizations that operate the test floor.\n<\/p>\n\n

    What Attendees Will Take Away<\/h3>\n\n
      \n
    • \n A concrete architectural picture of how AI agents move from \"smarter autocomplete inside the IDE\" to\n first-class operators of the test floor across every stage from EDA to SLT.\n <\/li>\n
    • \n A practical framing of the Unified Device Log as the spine that makes cross-stage investigation tractable \u2014\n including schema, identity propagation, and the customer IP boundary.\n <\/li>\n
    • \n A clear distinction between an agent that has hands (action surface), knowledge (domain-shaped tools), and\n memory (the device log) \u2014 and why all three are required for autonomy.\n <\/li>\n
    • \n Why simulation and digital-twin-led development is the natural next step once test programs become\n machine-authored artifacts rather than hand-edited files.\n <\/li>\n
    • \n An honest discussion of the open problems: hardware safety on live silicon, customer-IP protection,\n agent guardrails, and the organizational changes that come with intent-driven testing.\n <\/li>\n<\/ul>\n\n

      Audience and Relevance<\/h3>\n\n

      \nTest engineers, characterization engineers, yield and reliability leads, ATE platform architects, EDA and SLT\npractitioners, and engineering and executive leadership looking to catch the next stage of the semiconductor\ntest era.\n<\/p>\n\n

      \nParticularly relevant for organizations facing the cost of cross-stage data fragmentation and looking for a\ncredible path from today's IDE-centric workflows to AI-native, intent-driven test operations.\n<\/p><\/p>

      \nMykola Zakharchuk<\/strong> is Product Owner at Advantest with ten years of experience in semiconductor test.\nHe works at the intersection of generative AI and automated test, focusing on how large language models,\nagent frameworks, and open protocols such as the Model Context Protocol are reshaping the way test\nprograms are authored, executed, and debugged.\n<\/p>\n\n

      \nHis current work centers on the long-term vision for an agentic test platform spanning EDA through SLT,\nwith a common analytics layer and a Unified Device Log as its spine. He speaks regularly on the future of AI\nin semiconductor test.\n<\/p><\/p><\/details>\n

      \n\t\ucd08\ub85d - \uc804\uae30 (Korean)<\/summary>\n

      \ucd08\ub85d<\/h3>\n\n

      \n\uc624\ub298\ub0a0 \ubc18\ub3c4\uccb4 \ud14c\uc2a4\ud2b8\ub294 EDA, \uc6e8\uc774\ud37c \uc18c\ud2b8, \ud30c\uc774\ub110 \ud14c\uc2a4\ud2b8, \uc2dc\uc2a4\ud15c \ub808\ubca8 \ud14c\uc2a4\ud2b8(SLT), \uc2e0\ub8b0\uc131,\n\ud544\ub4dc\uc5d0 \uc774\ub974\uae30\uae4c\uc9c0 \uc11c\ub85c \ub2e8\uc808\ub41c \ub2e8\uacc4\ub4e4\uc758 \uc5f0\uc18d\uc73c\ub85c \uc6b4\uc601\ub418\uba70, \uac01 \ub2e8\uacc4\ub294 \uace0\uc720\uc758 \ud234\uacfc \ub370\uc774\ud130\ub85c\uadf8\n\ud3ec\ub9f7, \uadf8\ub9ac\uace0 \ubcc4\ub3c4\uc758 \uc5d4\uc9c0\ub2c8\uc5b4\ub9c1 \ud300\uc744 \uac00\uc9c0\uace0 \uc788\uc2b5\ub2c8\ub2e4.\n<\/p>\n\n

      \n\uadf8 \uacb0\uacfc\ub294 \uc5c5\uacc4\uc5d0 \uc798 \uc54c\ub824\uc838 \uc788\uc2b5\ub2c8\ub2e4. SLT \ub2e8\uacc4\uc758 \ubd88\ub7c9(escape)\uc774 \uc18c\ud2b8 \uc2dc\uadf8\ub2c8\ucc98\ub85c \uae54\ub054\ud558\uac8c\n\ucd94\uc801\ub418\ub294 \uacbd\uc6b0\ub294 \ub4dc\ubb3c\uace0, \ud2b9\uc131\ud654(characterization) \ub370\uc774\ud130\ub294 \uc218\uc728 \ubd84\uc11d\ub9c8\ub2e4 \uc218\uc791\uc5c5\uc73c\ub85c \uc7ac\uad6c\uc131\ub418\uba70,\n\uc5d4\uc9c0\ub2c8\uc5b4\uc758 \uac00\uc7a5 \uac12\ube44\uc2fc \uc5c5\ubb34\ub294 \ud14c\uc2a4\ud2b8 \uc2e4\ud589 \uc790\uccb4\uac00 \uc544\ub2c8\ub77c \uc5ec\ub7ec \ub2e8\uacc4\uc5d0 \uac78\uce5c \ubb38\ub9e5\uc744 \uc774\uc5b4 \ubd99\uc774\ub294\n\uc77c\uc785\ub2c8\ub2e4.\n<\/p>\n\n

      \n\ubcf8 \ubc1c\ud45c\ub294 \ud5a5\ud6c4 10\ub144\uc758 \ud14c\uc2a4\ud2b8\uc5d0 \ub300\ud574 \ub2e4\ub978 \ud615\ud0dc\ub97c \uc81c\uc548\ud569\ub2c8\ub2e4. \ud14c\uc2a4\ud130\ub294 \uacb0\uc815\ub860\uc801(deterministic)\n\uc2e4\ud589 \uc5d4\uc9c4\uc774 \ub418\uace0, IDE\ub294 \uc120\ud0dd \uc0ac\ud56d\uc774 \ub418\uba70, \ubd84\uc57c\ubcc4\ub85c \ud2b9\ud654\ub41c AI \uc5d0\uc774\uc804\ud2b8 \uc9d1\ub2e8 \u2014 \ud14c\uc2a4\ud2b8,\n\uc5f4(Thermal), \ud2b9\uc131\ud654, \uc218\uc728, \uc2e0\ub8b0\uc131, SLT, \uc560\ud50c\ub9ac\ucf00\uc774\uc158 \uc5d4\uc9c0\ub2c8\uc5b4\ub9c1 \u2014 \uc774 \ud1b5\ud569 \ubd84\uc11d \ud50c\ub7ab\ud3fc \uc704\uc5d0\uc11c,\nEDA\ubd80\ud130 \ud544\ub4dc \ubc18\ud488\uae4c\uc9c0 \uac01 \ub2e4\uc774(die)\ub97c \ub530\ub77c\ub2e4\ub2c8\ub294 \uacf5\ud1b5 \ub514\ubc14\uc774\uc2a4 \ub85c\uadf8(Device Log)\ub97c \uae30\ubc18\uc73c\ub85c\n\ub3d9\uc791\ud558\ub294 \u2018\uc0ac\uace0\ud558\ub294 \ud14c\uc2a4\ud2b8 \ud50c\ub85c\uc5b4(thinking test floor)\u2019\uc785\ub2c8\ub2e4.\n<\/p>\n\n

      \n\uc774\ub97c \uac00\ub2a5\ud558\uac8c \ud558\ub294 \ubca4\ub354 \uc911\ub9bd\uc801(vendor-neutral) 3\uacc4\uce35 \uc544\ud0a4\ud14d\ucc98\ub97c \uc18c\uac1c\ud569\ub2c8\ub2e4.\n<\/p>\n\n

        \n
      1. \n \uc5d4\uc9c0\ub2c8\uc5b4\uac00 \ud074\ub9ad\uc774 \uc544\ub2c8\ub77c \uc758\ub3c4(intent) \uc218\uc900\uc5d0\uc11c \uc870\uc885\ud558\ub294 \uc5d0\uc774\uc804\ud2b8 \ud50c\ub9bf(Agent Fleet)<\/strong>.\n <\/li>\n
      2. \n \uc758\ub3c4\ub97c \ub3c4\uba54\uc778\uc5d0 \ub9de\ucdb0\uc9c4 \ud234\uc744 \ud1b5\ud574 \uce21\uc815 \ub3d9\uc791\uc73c\ub85c \ubcc0\ud658\ud558\uace0 \ud558\ub4dc\uc6e8\uc5b4 \uc548\uc804 \ubc94\uc704(safety envelope)\ub97c\n \uad6c\uc870\uc801\uc73c\ub85c \uac15\uc81c\ud558\ub294 \uc5d0\uc774\uc804\ud2f1 \ucee8\ud2b8\ub864 \ud50c\ub808\uc778(Agentic Control Plane)<\/strong>.\n <\/li>\n
      3. \n \uae30\uacc4\uac00 \uc791\uc131\ud558\uace0 \uc11c\uba85\u00b7\ubc84\uc804 \uad00\ub9ac\ub41c \ud14c\uc2a4\ud2b8 \ud504\ub85c\uadf8\ub7a8\uc744 \uc218\uc6a9\ud558\ub294 \uc548\uc815\uc801 \uacc4\uc57d(contract)\uc744 \uac16\ucd98\n \ud5e4\ub4dc\ub9ac\uc2a4(headless) \uc2e4\ud589 \uacc4\uce35<\/strong>.\n <\/li>\n<\/ol>\n\n

        \n\uc774 \uc138 \uacc4\uce35\uc744 \ud558\ub098\ub85c \ubb36\ub294 \uac83\uc740 \ud1b5\ud569 \ub514\ubc14\uc774\uc2a4 \ub85c\uadf8(Unified Device Log)<\/strong>\ub85c,\n\uac01 \ub514\ubc14\uc774\uc2a4\uc758 \ud3c9\uc0dd \uc2dd\ubcc4\uc790\uc5d0 \uc5f0\uacb0\ub41c \uc2a4\ud0a4\ub9c8 \uae30\ubc18\uc758 \ucd94\uac00 \uc804\uc6a9(append-only)\u00b7\uace0\uac1d \uc18c\uc720 \uae30\ub85d\uc774\uba70,\n\ub2e8\uacc4 \uac04 \ubd84\uc11d\uc744 \ud558\ub098\uc758 \ud504\ub85c\uc81d\ud2b8\uc5d0\uc11c \ud558\ub098\uc758 \ucffc\ub9ac\ub85c \ubc14\uafd4 \ub193\uc2b5\ub2c8\ub2e4.\n<\/p>\n\n

        \n\ub610\ud55c \uc2e4\uc81c \uc2e4\ub9ac\ucf58\uc744 \ub2e4\ub8e8\uae30 \ud6e8\uc52c \uc804\uc5d0 \uc5d0\uc774\uc804\ud2b8\uac00 \uac00\uc0c1 \ud14c\uc2a4\ud130\uc640 \ub514\uc9c0\ud138 \ud2b8\uc708 \ub514\ubc14\uc774\uc2a4 \ubaa8\ub378\uc744\n\ub300\uc0c1\uc73c\ub85c \ubc18\ubcf5 \uac1c\ubc1c\uc744 \uc218\ud589\ud558\ub294 \uc2dc\ubbac\ub808\uc774\uc158 \uc8fc\ub3c4(simulation-led) \ud14c\uc2a4\ud2b8 \uac1c\ubc1c\ub85c\uc758 \uc804\ud658\uc744 \uc0b4\ud3b4\ubcf4\uace0,\n\uc774\uac83\uc774 \ud234\ub9c1, IP \uacbd\uacc4, \uace0\uac1d \uc2e0\ub8b0, \uadf8\ub9ac\uace0 \ud14c\uc2a4\ud2b8 \ud50c\ub85c\uc5b4\ub97c \uc6b4\uc601\ud558\ub294 \uc5d4\uc9c0\ub2c8\uc5b4\ub9c1 \uc870\uc9c1\uc5d0 \uc5b4\ub5a4 \uc758\ubbf8\ub97c\n\uac16\ub294\uc9c0 \ub17c\uc758\ud569\ub2c8\ub2e4.\n<\/p><\/p>

        \n\ubbf8\ucf5c\ub77c \uc790\ud558\ub974\ucd94\ud06c(Mykola Zakharchuk)<\/strong>\ub294 Advantest\uc758 \ud504\ub85c\ub355\ud2b8 \uc624\ub108(Product Owner)\ub85c,\n\ubc18\ub3c4\uccb4 \ud14c\uc2a4\ud2b8 \ubd84\uc57c\uc5d0\uc11c 10\ub144\uc758 \uacbd\ub825\uc744 \ubcf4\uc720\ud558\uace0 \uc788\uc2b5\ub2c8\ub2e4.\n<\/p>\n\n

        \n\uadf8\ub294 \uc0dd\uc131\ud615 AI\uc640 \uc790\ub3d9 \ud14c\uc2a4\ud2b8\uc758 \uc811\uc810\uc5d0\uc11c, \ub300\uaddc\ubaa8 \uc5b8\uc5b4 \ubaa8\ub378(LLM), \uc5d0\uc774\uc804\ud2b8 \ud504\ub808\uc784\uc6cc\ud06c,\n\uadf8\ub9ac\uace0 Model Context Protocol\uacfc \uac19\uc740 \uac1c\ubc29\ud615 \ud504\ub85c\ud1a0\ucf5c\uc774 \ud14c\uc2a4\ud2b8 \ud504\ub85c\uadf8\ub7a8\uc758 \uc791\uc131\u00b7\uc2e4\ud589\u00b7\ub514\ubc84\uae45\n\ubc29\uc2dd\uc744 \uc5b4\ub5bb\uac8c \ubcc0\ud654\uc2dc\ud0a4\uace0 \uc788\ub294\uc9c0\uc5d0 \uc8fc\ubaa9\ud558\uba70 \uc5f0\uad6c\ud558\uace0 \uc788\uc2b5\ub2c8\ub2e4.\n<\/p>\n\n

        \n\ud604\uc7ac\ub294 EDA\ubd80\ud130 SLT\uae4c\uc9c0 \uc544\uc6b0\ub974\ub294 \uc5d0\uc774\uc804\ud2b8 \uae30\ubc18 \ud14c\uc2a4\ud2b8 \ud50c\ub7ab\ud3fc\uacfc, \uadf8 \uc911\uc2ec\ucd95\uc774 \ub418\ub294 \uacf5\ud1b5 \ubd84\uc11d\n\uacc4\uce35 \ubc0f \ud1b5\ud569 \ub514\ubc14\uc774\uc2a4 \ub85c\uadf8(Unified Device Log)\uc5d0 \ub300\ud55c \uc7a5\uae30 \ube44\uc804\uc5d0 \uc9d1\uc911\ud558\uace0 \uc788\uc2b5\ub2c8\ub2e4.\n<\/p>\n\n

        \n\uadf8\ub294 \ubc18\ub3c4\uccb4 \ud14c\uc2a4\ud2b8 \ubd84\uc57c\uc5d0\uc11c AI\uc758 \ubbf8\ub798\uc5d0 \ub300\ud574 \uc815\uae30\uc801\uc73c\ub85c \uac15\uc5f0\ud558\uace0 \uc788\uc2b5\ub2c8\ub2e4.\n<\/p><\/p><\/details>\n<\/div>\n

        \n
        \n“A HW or SW approach to Power Supply Rail Multi Switching on a Device Power Supply (DPS)” \n<\/div>\n
        \n
        \n
        \nThomas Angelo C. \"Thomas\" Abiog\n <\/div>\n\t
        \nElevATE Semiconductor\n\t <\/div>\n <\/div>\n<\/div>\n
        \n\tAbstract (English)<\/summary>\n

        \nThis paper presents a hardware (HW)<\/strong> and software (SW)<\/strong> approach to Power Supply Rail Multi Switching<\/strong> on a Device Power Supply (DPS)<\/strong> using multiple voltage rails. Implemented with the Whitney DPS<\/strong> as a demonstration platform, the system selects the most efficient voltage rail based on output demand to reduce power loss, lower heat dissipation, and improve thermal performance. The design supports both hardware-based comparator logic<\/strong> and software-based digital control<\/strong> for flexible envelope-tracking operation.\n<\/p>\n\n

        \nThe solution uses make-before-break rail switching<\/strong>, eFuse protection<\/strong>, buffered voltage sensing<\/strong>, and threshold-based control<\/strong> to maintain continuous operation during voltage transitions. Results from both hardware and software demonstrations at 200 mA<\/strong>, 500 mA<\/strong>, and up to 1 A<\/strong> show stable rail handoff and reliable output regulation across changing load conditions.\n<\/p>\n\n

        \nThese results demonstrate that the proposed Envelope-Tracking Power Supply (ETPS)<\/strong> is an effective solution for improving power efficiency<\/em>, thermal management<\/em>, and system reliability<\/em> in high-voltage DPS applications.\n<\/p><\/p>

        <\/p><\/details>\n<\/div>\n<\/div>\n\t \n<\/div>

        <\/div><\/div><\/div>

        17:15<\/h1>\n<\/div><\/div><\/div><\/div>

        Lucky Draw<\/strong><\/h1>\n

        Door prizes for randomly selected attendees<\/span>
        \n(Must be present to win \/ void where prohibited)<\/p><\/span><\/div><\/div><\/div><\/div><\/div><\/div>

        17:45<\/h1>\n<\/div><\/div><\/div><\/div>

        TestConX EXPO Closes \/ Event Adjourns<\/strong><\/h1>\n<\/div><\/div><\/div><\/div><\/div><\/div>
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