{"id":9090,"date":"2026-08-19T18:13:25","date_gmt":"2026-08-20T01:13:25","guid":{"rendered":"https:\/\/www.testconx.org\/premium\/?page_id=9090"},"modified":"2026-09-08T13:27:04","modified_gmt":"2026-09-08T20:27:04","slug":"testconx-korea-2026","status":"publish","type":"page","link":"https:\/\/www.testconx.org\/premium\/testconx-korea-2026\/","title":{"rendered":"TestConX Korea 2026"},"content":{"rendered":"
\"Image\"<\/span>

Suwon, South Korea - October 27, 2026<\/h1>\n<\/div><\/div><\/div>

SINTEX Convention Center<\/a><\/div>\n
(At LA VIE D'OR Resort)<\/a><\/div>\n
141-36 Botong-ri, Jeongnam-myeon, Hwaseong-si,<\/div>\n
Gyeonggi-do, South Korea<\/div><\/h1>\n<\/div><\/div><\/div><\/div><\/div><\/div><\/div>
Register<\/span><\/div><\/div><\/a>
EXPO<\/span><\/div><\/div><\/a>

TestConX<\/span><\/a>, over the course of its twenty-seven-year history, has established itself as the preeminent event for test consumables, test cell integration, and test operations. The program scope includes packaged semiconductor “final” test, burn-in, system level test, and beyond to encompass all practical aspects of electronics testing such as validation, advanced packaging testing, module test, and finished product test. <\/span><\/p>\n

Please join us for our 4th annual TestConX Korea! Don’t miss this opportunity to be part of TestConX as we connect a larger community of test professionals and to participate in this excellent event!<\/span><\/p>\n

 <\/p><\/div>

<\/div><\/div><\/div>

Tuesday October 27, 2026<\/h1>\n<\/div><\/div><\/div>

9:00<\/h1>\n<\/div><\/div><\/div><\/div>
\n
\n
Welcome<\/div><\/div>
<\/div>
<\/div>

<\/p><\/div>

\n
\n“Opening Remarks” \n<\/div>\n
\n
\n
\nIra Feldman\n <\/div>\n\t
\nFeldman Engineering\n\t <\/div>\n <\/div>\n<\/div>\n<\/div>\n<\/div>\n\t \n<\/div><\/div><\/div>

9:15<\/h1>\n<\/div><\/div><\/div><\/div>
\n
\n
Technical 1<\/div><\/div>
<\/div>
<\/div>

<\/p><\/div>

\n
\n“Electrical Performance Comparison between Coaxial and non-coaxial Elastomer Test Socket” \n
“\ub3d9\ucd95\/\ube44\ub3d9\ucd95 \uad6c\uc870\uc758 \uc5d8\ub77c\uc2a4\ud1a0\uba38 \ud14c\uc2a4\ud2b8 \uc18c\ucf13\uc758 \uc131\ub2a5 \ube44\uad50” \n<\/div>\n
\n
\n
\nJunyong Park\n <\/div>\n\t
\nKyung Hee University\n\t <\/div>\n <\/div>\n
\n
\nJimin Song\n <\/div>\n\t
\nKyung Hee University\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract - Biography (English)<\/summary>\n

High-speed semiconductor testing increasingly requires test sockets with improved signal integrity and electrical performance.
\nThis study compares the electrical characteristics of coaxial and non-coaxial elastomer test socket structures for high-speed test applications.
\nThe coaxial structure provides a controlled signal and ground configuration, enabling improved impedance control and reduced electromagnetic coupling between adjacent signal paths.
\nElectrical performance is evaluated in terms of insertion loss, return loss, crosstalk, and impedance characteristics over a wide frequency range.
\nThe results demonstrate the impact of socket interconnect architecture on high-frequency signal transmission and identify the performance advantages and design considerations of the coaxial configuration.
\nThese findings provide practical guidance for test socket design targeting next-generation high-speed and high-frequency semiconductor devices.<\/p><\/p>

Jimin Song is currently pursuing the M.S. degree in Semiconductor Engineering at Kyung Hee University, South Korea. His research focuses on electrical validation and signal integrity analysis of high-speed chiplet interconnects and advanced semiconductor packages.<\/p><\/p><\/details>\n

\n\t\ucd08\ub85d - \uc804\uae30 (Korean)<\/summary>\n

\uace0\uc18d \ubc18\ub3c4\uccb4 \ud14c\uc2a4\ud2b8 \ud658\uacbd\uc5d0\uc11c\ub294 \uc6b0\uc218\ud55c \uc2e0\ud638 \ubb34\uacb0\uc131(Signal Integrity)\uacfc \uc804\uae30\uc801 \ud2b9\uc131\uc744 \uac16\ub294 \ud14c\uc2a4\ud2b8 \uc18c\ucf13\uc758 \uc911\uc694\uc131\uc774 \uc810\ucc28 \uc99d\uac00\ud558\uace0 \uc788\ub2e4.
\n\ubcf8 \uc5f0\uad6c\uc5d0\uc11c\ub294 \uace0\uc18d \ud14c\uc2a4\ud2b8 \uc751\uc6a9\uc744 \uc704\ud55c \ub3d9\ucd95(Coaxial) \ubc0f \ube44\ub3d9\ucd95(Non-coaxial) \uc5d8\ub77c\uc2a4\ud1a0\uba38 \ud14c\uc2a4\ud2b8 \uc18c\ucf13 \uad6c\uc870\uc758 \uc804\uae30\uc801 \ud2b9\uc131\uc744 \ube44\uad50 \ubd84\uc11d\ud558\uc600\ub2e4.
\n\ub3d9\ucd95 \uad6c\uc870\ub294 \uc2e0\ud638\uc120\uacfc \uc811\uc9c0\uc758 \ubc30\uce58\ub97c \uc81c\uc5b4\ud568\uc73c\ub85c\uc368 \uc548\uc815\uc801\uc778 \uc784\ud53c\ub358\uc2a4 \ud2b9\uc131\uc744 \uad6c\ud604\ud558\uace0 \uc778\uc811 \uc2e0\ud638 \uac04 \uc804\uc790\uae30\uc801 \uacb0\ud569\uc744 \uac10\uc18c\uc2dc\ud0ac \uc218 \uc788\ub2e4.
\n\ub450 \uad6c\uc870\uc758 \uc804\uae30\uc801 \uc131\ub2a5\uc744 \uc0bd\uc785\uc190\uc2e4(Insertion Loss), \ubc18\uc0ac\uc190\uc2e4(Return Loss), \ub204\ud654(Crosstalk) \ubc0f \uc784\ud53c\ub358\uc2a4 \ud2b9\uc131\uc744 \uc911\uc2ec\uc73c\ub85c \uad11\ub300\uc5ed \uc8fc\ud30c\uc218 \uc601\uc5ed\uc5d0\uc11c \ud3c9\uac00\ud558\uc600\ub2e4.
\n\uc774\ub97c \ud1b5\ud574 \ud14c\uc2a4\ud2b8 \uc18c\ucf13\uc758 \uc778\ud130\ucee4\ub125\ud2b8 \uad6c\uc870\uac00 \uace0\uc8fc\ud30c \uc2e0\ud638 \uc804\uc1a1 \ud2b9\uc131\uc5d0 \ubbf8\uce58\ub294 \uc601\ud5a5\uc744 \ubd84\uc11d\ud558\uace0, \ub3d9\ucd95 \uad6c\uc870\uac00 \uc81c\uacf5\ud558\ub294 \uc804\uae30\uc801 \uc131\ub2a5\uc0c1\uc758 \uc774\uc810\uacfc \uc8fc\uc694 \uc124\uacc4 \uace0\ub824\uc0ac\ud56d\uc744 \uc81c\uc2dc\ud558\uc600\ub2e4.
\n\ubcf8 \uc5f0\uad6c \uacb0\uacfc\ub294 \ucc28\uc138\ub300 \uace0\uc18d\u00b7\uace0\uc8fc\ud30c \ubc18\ub3c4\uccb4 \ud14c\uc2a4\ud2b8\ub97c \uc704\ud55c \uc5d8\ub77c\uc2a4\ud1a0\uba38 \ud14c\uc2a4\ud2b8 \uc18c\ucf13 \uc124\uacc4 \ubc0f \ucd5c\uc801\ud654\uc5d0 \uc2e4\uc9c8\uc801\uc778 \uac00\uc774\ub4dc\ub77c\uc778\uc744 \uc81c\uacf5\ud560 \uc218 \uc788\ub2e4.<\/p><\/p>

\ubcf8 \ubc1c\ud45c\uc790 \uc1a1\uc9c0\ubbfc \ud559\uc0dd\uc740 \ud604\uc7ac \uacbd\ud76c\ub300\ud559\uad50 \ubc18\ub3c4\uccb4\uacf5\ud559\uacfc \uc11d\uc0ac\uacfc\uc815\uc5d0 \uc7ac\ud559 \uc911\uc774\ub2e4. \uc8fc\uc694 \uc5f0\uad6c \ubd84\uc57c\ub294 \uace0\uc18d Chiplet Interconnect\uc640 \ucca8\ub2e8 \ubc18\ub3c4\uccb4 \ud328\ud0a4\uc9c0\uc758 \uc804\uae30\uc801 \uac80\uc99d \ubc0f Signal Integrity \ubd84\uc11d\uc774\ub2e4.<\/p><\/p><\/details>\n<\/div>\n

\n
\n“Design optimization of Lightweight Metal Trays in High-Temperature Reflow Processes of Advanced HBM Packages” \n
“ \uc2e0\ub8b0\uc131 \uac80\uc99d \uace0\uc628 \ub9ac\ud50c\ub85c\uc6b0 \uacf5\uc815\uc6a9 HBM \uba54\ud0c8 \ud2b8\ub808\uc774\uc758 \uacbd\ub7c9\ud654 \uc124\uacc4 \ucd5c\uc801\ud654” \n<\/div>\n
\n
\n
\nGyu-Yeol Kim\n <\/div>\n\t
\nSamsung\n\t <\/div>\n <\/div>\n
\n
\nJaewoong Choi\n <\/div>\n\t
\nSamsung\n\t <\/div>\n <\/div>\n
\n
\nHyunjae Lee\n <\/div>\n\t
\nSamsung\n\t <\/div>\n <\/div>\n
\n
\nInjae Lee\n <\/div>\n\t
\nsamsung\n\t <\/div>\n <\/div>\n
\n
\nWonhong Choi\n <\/div>\n\t
\nSamsung\n\t <\/div>\n <\/div>\n
\n
\nJeongHwan Kim\n <\/div>\n\t
\nSamsung\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract - Biography (English)<\/summary>\n

As large packages such as HBM see wider adoption, the metal trays used in high-temperature reflow processes for reliability testing can cause thermal damage to transfer components, such as the equipment's internal conveyor belts, creating a need for tray temperature-reduction design technology. This study proposes an optimal design that reduces the tray's heat capacity through lightweight design, thereby lowering the post-reflow tray temperature. The approach is developed and validated through finite element analysis (FEA) and prototype evaluation.<\/p>\n<\/p>

Gyu-Yeol Kim received his B.S. degree in Electrical Engineering from Kyunghee University, Suwon, Korea, in 2000, and his M.S. and Ph.D. degrees in Electrical Engineering from Sungkyunkwan University, Suwon, Korea, in 2008 and 2017, respectively. His current research interests include the design of memory package boards, sockets, and probe cards. Since 2000, he has been with Samsung Electronics, where he is a Principal Engineer of the EDS Test Technology Group.<\/p>\n<\/p><\/details>\n

\n\t\ucd08\ub85d - \uc804\uae30 (Korean)<\/summary>\n

HBM\uacfc \uac19\uc740 \ub300\ud615 \ud328\ud0a4\uc9c0\uc758 \uc801\uc6a9 \ud655\ub300\uc5d0 \ub530\ub77c \uc2e0\ub8b0\uc131 \ud3c9\uac00\ub97c \uc704\ud55c \uace0\uc628 \ub9ac\ud50c\ub85c\uc6b0 \uacf5\uc815\uc5d0 \uc0ac\uc6a9\ub418\ub294 \uba54\ud0c8 \ud2b8\ub808\uc774\ub97c \uc774\uc6a9\ud55c \uc7a5\ube44 \ub0b4\ubd80 \ubc18\uc1a1 \ubca8\ud2b8 \ub4f1 \uc774\uc1a1 \ubd80\ud488\uc758 \uc5f4\uc190\uc0c1\uc744 \uc720\ubc1c\ud560 \uc218 \uc788\uc5b4 \ud2b8\ub808\uc774 \uc628\ub3c4 \uc800\uac10 \uc124\uacc4 \uae30\uc220\uc774 \uc694\uad6c\ub41c\ub2e4. \ubcf8 \uc5f0\uad6c\uc5d0\uc11c\ub294 \uba54\ud0c8 \ud2b8\ub808\uc774\uc758 \uacbd\ub7c9\ud654\ub97c \ud1b5\ud574 \uc5f4\uc6a9\ub7c9\uc744 \uac10\uc18c\uc2dc\ucf1c \ub9ac\ud50c\ub85c\uc6b0 \uc774\ud6c4 \ud2b8\ub808\uc774 \uc628\ub3c4\ub97c \ub0ae\ucd9c \uc218 \uc788\ub3c4\ub85d \uc720\ud55c\uc694\uc18c\ud574\uc11d\uacfc \uc2dc\uc81c\ud488 \ud3c9\uac00\ub97c \ud1b5\ud55c \ucd5c\uc801 \uc124\uacc4 \ubc29\uc548\uc744 \uc81c\uc548\ud55c\ub2e4.<\/p>\n<\/p>

\uacbd\ud76c\ub300\ud559\uad50 \uc804\uc790\uacf5\ud559\uacfc(2000), \uc131\uade0\uad00\ub300\ud559\uad50 \uc804\uae30\uc804\uc790\uacf5\ud559\uacfc \uc11d\uc0ac(2008), \ubc15\uc0ac(2017), 2000\ub144 2\uc6d4 ~ \ud604\uc7ac: \uc0bc\uc131\uc804\uc790(\uba54\ubaa8\ub9ac) \uc218\uc11d\uc5f0\uad6c\uc6d0. \uad00\uc2ec\ubd84\uc57c: package test board, socket, probe card, memory test.<\/p>\n<\/p><\/details>\n<\/div>\n<\/div>\n\t \n<\/div><\/div><\/div>

10:15<\/h1>\n<\/div><\/div><\/div><\/div>

Break & Networking<\/strong><\/h1>\nEnjoy time to meet with the presenters and network while refreshments are served.<\/span><\/span><\/div><\/div><\/div>
<\/div><\/div><\/div>

10:45<\/h1>\n<\/div><\/div><\/div><\/div>
\n
\n
Keynote<\/div><\/div>
<\/div>
<\/div>

<\/p><\/div><\/div>\n\t \n

\"Prof.<\/span><\/div>

Prof. Donghwan Ahn<\/strong> is presently a professor in the School of Materials Science and Engineering at Kookmin University, Seoul, Korea. Prior to joining Kookmin University, he was a Senior Research Engineer and a team leader of Advanced Silicon Photonics and Electronics Lab at Samsung Electronics U.S. R&D Center (SAIT-USA). He received B.S. and M.S. degrees in materials science and engineering from Seoul National University, South Korea, in 1996 and 2000, respectively.<\/p><\/div><\/div><\/div><\/div>

He earned his Ph.D. degree from Massachusetts Institute of Technology (MIT) in 2007, under the guidance of Prof. Lionel C. Kimerling. In his Ph.D. dissertation entitled “Intra-chip Clock Signal Distribution via Si-based Optical Interconnect”, he pioneered an H-tree waveguide network and demonstrated the world’s first waveguide-integrated germanium photodetector, which is now widely adopted in optical engine chiplets for Co-Package Optics (CPO). Prior to joining Samsung, he was an NSF\/ASEE Research Fellow at Bell Laboratories, Alcatel-Lucent, where he conducted research on silicon CMOS-compatible photonic devices in the Advanced Photonic Integration group, and a Senior Research Scientist at Astrowatt Inc., a solar cell start-up company in Austin, Texas. His current research interests include germanium-based photonic and electronic devices, optical interconnect and packaging for AI and high-performance computing, and photonic integrated circuits for quantum computing chip.<\/p><\/div><\/div><\/div><\/div>

<\/div><\/div><\/div>

11:45<\/h1>\n<\/div><\/div><\/div><\/div>

Lunch & EXPO<\/strong><\/h1>\nEnjoy the delicious hot buffet lunch and networking time. Then take the time to explore the TestConX EXPO. There will be many great exhibits to connect electronic test professionals to solutions. You will be certain to see something new or meet someone new. As attendees to TestConX know, there is always excellent food, drinks, and time for attendees to network with exhibitors! TestConX EXPO will open at 11:45 and will remain open throughout the afternoon until 18:00
<\/span><\/span><\/div><\/div><\/div>
<\/div><\/div><\/div>

13:30<\/h1>\n<\/div><\/div><\/div><\/div><\/div><\/div>
<\/div>
\n
\n
Distinguished<\/div><\/div>
<\/div>
<\/div>

<\/p><\/div>

\n
\n“Where Does Demand Come From, and Who Gets the Bill? - The Position of Back-End Semiconductor Manufacturing in the AI Era” \n
“\uc218\uc694\ub294 \uc5b4\ub514\uc5d0\uc11c \uc624\uace0, \uccad\uad6c\uc11c\ub294 \ub204\uad6c\uc5d0\uac8c \uac00\ub098? -AI \uc2dc\ub300 \ud6c4\uacf5\uc815\uc758 \uc704\uce58” \n<\/div>\n
\n
\n
\nJihoon Jang\n <\/div>\n\t
\nGagetseoul Media\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract (English)<\/summary>\n

AI computing investment has accelerated demand for AI accelerators and high-bandwidth memory (HBM). Yet the point at which that demand becomes shippable product lies in advanced packaging and test. Larger dies, stacked HBM, and chiplet integration are increasing test time, yield risk, and capital intensity\u2014reshaping both the role of back-end manufacturing and its cost structure.<\/p>\n\n

This presentation traces the path from data-center capital expenditure to demand for accelerators, memory production, advanced packaging, and test. It also examines where the added complexity and cost ultimately reside: with foundries, memory manufacturers, OSAT providers, test-equipment suppliers, cloud operators, or end users of AI services. In the AI era, back-end manufacturing is no longer merely the final step in semiconductor production; it has become a strategic gatekeeper of shippable volume, delivery capability, and profitability.<\/p><\/p>

<\/p><\/details>\n

\n\t\ucd08\ub85d (Korean)<\/summary>\n

AI \ucef4\ud4e8\ud305 \ud22c\uc790\ub294 \uac00\uc18d\uae30\uc640 HBM \uc218\uc694\ub97c \ub04c\uc5b4\uc62c\ub838\uc9c0\ub9cc, \uadf8 \uc218\uc694\uac00 \uc2e4\uc81c \ucd9c\ud558\ub85c \uc804\ud658\ub418\ub294 \uc9c0\uc810\uc740 \ucca8\ub2e8 \ud328\ud0a4\uc9d5\uacfc \ud14c\uc2a4\ud2b8\ub2e4. \ub300\ud615 \ub2e4\uc774, HBM \uc801\uce35, \uce69\ub81b \ud1b5\ud569\uc740 \ud14c\uc2a4\ud2b8 \uc2dc\uac04\u00b7\uc218\uc728 \ub9ac\uc2a4\ud06c\u00b7\uc124\ube44 \ubd80\ub2f4\uc744 \ud0a4\uc6b0\uba70 \ud6c4\uacf5\uc815\uc758 \uc5ed\ud560\uacfc \ube44\uc6a9 \uad6c\uc870\ub97c \ubc14\uafb8\uace0 \uc788\ub2e4.<\/p>\n\n

\uc774 \ubc1c\ud45c\ub294 \ub370\uc774\ud130\uc13c\ud130 CAPEX\uc5d0\uc11c \uac00\uc18d\uae30\u00b7\uba54\ubaa8\ub9ac \uc0dd\uc0b0, \ud328\ud0a4\uc9d5\u00b7\ud14c\uc2a4\ud2b8 \uc218\uc694\ub85c \uc774\uc5b4\uc9c0\ub294 \uacbd\ub85c\ub97c \ucd94\uc801\ud55c\ub2e4. \ub610\ud55c \ub298\uc5b4\ub09c \ubcf5\uc7a1\uc131\uacfc \ube44\uc6a9\uc774 \ud30c\uc6b4\ub4dc\ub9ac, \uba54\ubaa8\ub9ac \uc5c5\uccb4, OSAT, \uc7a5\ube44 \uc5c5\uccb4, \ud074\ub77c\uc6b0\ub4dc \uc0ac\uc5c5\uc790, \uadf8\ub9ac\uace0 \ucd5c\uc885 AI \uc0ac\uc6a9\uc790 \uac00\uc6b4\ub370 \ub204\uad6c\uc5d0\uac8c \uadc0\uc18d\ub418\ub294\uc9c0 \uc0b4\ud3b4\ubcf8\ub2e4. AI \uc2dc\ub300\uc758 \ud6c4\uacf5\uc815\uc740 \ub354 \uc774\uc0c1 \uc81c\uc870\uc758 \ub9c8\uc9c0\ub9c9 \ub2e8\uacc4\uac00 \uc544\ub2c8\ub77c, \ucd9c\ud558 \uac00\ub2a5 \ubb3c\ub7c9\uacfc \uc218\uc775\uc131\uc744 \uacb0\uc815\ud558\ub294 \uc804\ub7b5\uc801 \uad00\ubb38\uc774 \ub418\uace0 \uc788\ub2e4.<\/p><\/p>

<\/p><\/details>\n<\/div>\n<\/div>\n\t \n

\"Image\"<\/span><\/div>

\uac00\uc82f\uc11c\uc6b8 \ubbf8\ub514\uc5b4\uc758 \uc7a5\uc9c0\ud6c8 \ub300\ud45c\ub294 \ud55c\uad6d\uc678\uad6d\uc5b4\ub300\ud559\uad50\ub97c \uc878\uc5c5\ud55c \ud6c4 \ud55c\ud654\uadf8\ub8f9 \uacf5\ucc44\ub85c \ucee4\ub9ac\uc5b4\ub97c \uc2dc\uc791\ud588\ub2e4. \uc804\ub7b5\/\uae30\ud68d\ud300\uc5d0\uc11c \uadfc\ubb34\ud558\uba70 IT \ubd84\uc57c\uc758 \uba38\ucc9c\ub2e4\uc774\uc800\ub85c \ube0c\ub79c\ub4dc\uc640 \uc0c1\ud488\uc744 \uc804\uac1c\ud558\uc600\ub2e4. \uc774\ud6c4 \uacbd\uc81c\uc9c0 \uc774\ucf54\ub178\ubbf8 \uc870\uc120\uc758 IT\uc804\ubb38 \uce7c\ub7fc\ub2c8\uc2a4\ud2b8\ub85c \uc5c5\uacc4\uc758 \uc2dc\ud669\uacfc \uc120\ud589\uae30\uc220\ub4e4\uc5d0 \ub300\ud55c \uae4a\uc774 \uc788\ub294 \uc778\uc0ac\uc774\ud2b8\ub97c \uacf5\uc720\ud574\uc654\ub2e4. \ud604\uc7ac\ub294 \uc720\ud29c\ube0c \ucc44\ub110 \uac00\uc82f\uc11c\uc6b8\uc744 \ud1b5\ud574 \uc0c1\ud488\uacfc \ube0c\ub79c\ub4dc, \uae30\uc220\uacfc \uc2dc\ud669\uc744 \uade0\ud615\uac10\uc788\uac8c \uc870\ub9dd\ud558\ub294 \uc601\uc0c1 \uce7c\ub7fc\uc744 \uc81c\uacf5\ud558\uace0 \uc788\ub2e4.<\/p><\/div><\/div><\/div><\/div>

Jihoon Jang, the CEO of Gadgetseoul Media, developed and narrates the highly informative and popular Gadgetseoul YouTube channel<\/a> focused on semiconductors and technology. Prior to which he was an Information Technology columnist for Economy<\/i> Chosun<\/i>. He started his career at Hanwha group as an IT\/Tech Merchandiser, managing and promoting many brands and products on the Strategy\/Planning team after completing his studies at Hankuk University of Foreign Studies.<\/p><\/div>

\n
\n
Market<\/div><\/div>
<\/div>
<\/div>

<\/p><\/div>

\n
\n“How high-performance packaging is reshaping the test and burn-in socket market.” \n<\/div>\n
\n
\n
\nJohn West\n <\/div>\n\t
\nYole Group\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tBiography (English)<\/summary>\n

<\/p>

John West<\/strong> is a Senior Director of the Semiconductor Subsystems and Test Division at Yole Group. He has over 20 years of industry experience and a successful track record in various strategy and consulting projects. John has a Bachelor's degree in Medical Physics from King's College London and an MBA from Cranfield School of Management.<\/p><\/p><\/details>\n

\n\t\uc804\uae30 (Korean)<\/summary>\n

<\/p>

John West<\/strong>\ub294 Yole Group\uc758 Semiconductor Subsystems and Test Division\uc758 Senior Director\uc774\ub2e4. \uadf8\ub294 20\ub144 \uc774\uc0c1\uc758 \uc5c5\uacc4 \uacbd\ud5d8\uacfc \ub2e4\uc591\ud55c \uc804\ub7b5 \ubc0f \ucee8\uc124\ud305 \ud504\ub85c\uc81d\ud2b8\uc5d0\uc11c \uc131\uacf5\uc801\uc778 \uc2e4\uc801\uc744 \ubcf4\uc720\ud558\uace0 \uc788\ub2e4. John\uc740 King's College London\uc5d0\uc11c \uc758\ub8cc \ubb3c\ub9ac\ud559 \ud559\uc0ac \ud559\uc704\ub97c \ucde8\ub4dd\ud588\uc73c\uba70 Cranfield School of Management\uc5d0\uc11c MBA\ub97c \ucde8\ub4dd\ud588\ub2e4.<\/p>\n<\/p><\/details>\n<\/div>\n<\/div>\n\t \n<\/div><\/div><\/div>

14:45<\/h1>\n<\/div><\/div><\/div><\/div>

Posters & EXPO<\/strong><\/h1>\nEnjoy time to meet with the presenters and network while refreshments are served.<\/span><\/span><\/div><\/div><\/div>
\n
\n
Posters<\/div><\/div>
<\/div>
<\/div>

<\/p><\/div>

\n
\n“Testing the 20 bit Digital to Analog Converter using a Bench top rack and stack system” \n<\/div>\n
\n
\n
\nRajesh Sur\n <\/div>\n\t
\nElevate\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract (English)<\/summary>\n

Testing of 20-bit digital-to-analog converters (DACs) is typically performed using automated test equipment, which is costly and requires complex handler configuration. As an alternative, the rack-and-stack method facilitates testing without such expensive equipment by employing a digital pattern generator to supply the required digital codes. Comprehensive evaluation of a 20-bit DAC necessitates 1,048,576 digital codes. Although this method increases test duration and reduces product margin, this study presents a methodology utilizing a desktop rack-and-stack system to generate digital patterns, apply them to a 20-bit DAC, and measure the resulting output voltage.<\/p>\n\n

The output voltage is measured with an integrated oscilloscope, and a Python script is implemented to assess differential nonlinearity (DNL), integral nonlinearity (INL), offset error, and gain error. The same rack-and-stack benchtop system is used to describe the methodology for measuring power supply rejection ratio (PSRR). The measurement system includes a network analyzer capable of sweeping the ripple frequency in under thirty minutes and generating a PSRR report. Software algorithms for PSRR measurement are detailed, and the assessment of AC characteristics of a 20-bit DAC using the rack-and-stack test system is also addressed.<\/p>\n\n

The methodology to reduce ripple caused by di\/dt during power system activation is discussed. Additionally, the use of a Faraday cage is examined to minimize radio frequency interference during the measurement of DC and AC parameters of digital-to-analog converters.<\/p><\/p>

<\/p><\/details>\n<\/div>\n

\n
\n“Precision DAC converter testing” \n<\/div>\n
\n
\n
\nRajesh Sur\n <\/div>\n\t
\nElevate\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract (English)<\/summary>\n

Accurate testing of 12-, 16-, and 20-bit Digital-to-Analog Converters requires a precision voltage supply to measure differential non-linearity, integral non-linearity, gain error, and offset error. This paper details the delivery of precise on-board analog, digital, and reference voltages using a highly efficient 95% buck-boost converter.<\/p>\n\n

The described DC-DC converter features an enable pin for power sequencing, which can be controlled via a switch or a microcontroller's general-purpose input\/output (GPIO) pin. Minor voltage drops may result from the board's inherent IR drop. The methodology uses an 8-bit Digital-to-Analog Converter (DAC) in the feedback path to ensure precise voltage delivery to the device under test. In contrast to conventional DC-DC converters that rely on feedback resistors, integrating an 8-bit DAC simplifies voltage control.<\/p>\n\n

Further technical details are presented in subsequent sections. Within the graphical user interface (GUI), the 8-bit DAC control bit should be set before applying a precise voltage to the integrated circuit pins. The DC-DC converter can deliver up to 3.87 V at 5 A and support up to 15 converters on a single test board, offering a cost-effective solution.<\/p><\/p>

<\/p><\/details>\n<\/div>\n<\/div>\n\t \n

<\/div><\/div><\/div>

15:45<\/h1>\n<\/div><\/div><\/div><\/div>
\n
\n
Technical 2<\/div><\/div>
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<\/div>

<\/p><\/div>

\n
\n“Diagnosing SOA-Induced Aging Drift in Analog Pin Electronics: Implications for AI and HPC Test” \n
“\u8bca\u65ad\u6a21\u62df\u5f15\u811a\u7535\u5b50\u5668\u4ef6\u4e2d\u7531SOA\u5f15\u8d77\u7684\u8001\u5316\u6f02\u79fb\uff1a\u5bf9AI\u4e0eHPC\u6d4b\u8bd5\u7684\u542f\u793a” \n
“Analog Pin Electronics\uc758 SOA \uc720\ubc1c Aging Drift \uc9c4\ub2e8: AI \ubc0f HPC \ud14c\uc2a4\ud2b8\uc5d0 \ub300\ud55c \uc2dc\uc0ac\uc810” \n<\/div>\n
\n
\n
\nHailin Wang\n <\/div>\n\t
\nElevATE Semiconductor\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract - Biography (English)<\/summary>\n

\nSilent Data Corruption (SDC)<\/strong> and post-deployment hardware faults have emerged as significant reliability concerns for hyperscale AI and HPC infrastructure, with recent industry reports from Google, Meta, and the Open Compute Project (OCP) highlighting defects that pass manufacturing test but only manifest under specific bias conditions or after extended operation. The published case studies are predominantly digital. In this study, we examine the same failure class in an analog Automated Test Equipment (ATE)<\/strong> pin electronics ASIC, devices that perform final test on AI and HPC silicon.\n<\/p>\n\n

\nA customer reported progressive VCOM threshold drift<\/strong> on a 256-channel application, affecting approximately 50%<\/strong> of channels and continuing past -900 mV<\/strong> with no observable stabilization. All affected devices had passed final test before production. Failing devices were inspected, and results from initial visual inspection, ATE re-test, and emission microscopy were inconclusive. Bench characterization across 50 devices<\/strong> spanning multiple lots and date codes confirmed that the drift was reproducible and exhibited strong dependence on register configuration and operating temperature but evaded standard production screening due to its time-dependent nature.\n<\/p>\n\n

\nFailure analysis techniques such as Focused Ion Beam (FIB)<\/strong> produced misleading initial results. Severing a capacitor and diode in the comparator path arrested the drift, which initially appeared to identify the offending components. A subsequent control FIB cutting non-functional metal also halted the drift, demonstrating that the FIB process itself was perturbing the measurement rather than the targeted devices. This sensitivity to invasive characterization is a notable hazard for this defect class and constrains the design of subsequent debug experiments.\n<\/p>\n\n

\nRoot cause was traced to Safe Operating Area (SOA)<\/strong> violations within the analog comparator. Floating-node conditions in one register state and an over-stressed gain-stage VGS<\/sub><\/strong> in another subjected gate oxides to chronic overstress, accelerating Hot Carrier Injection (HCI)<\/strong> and Bias Temperature Instability (BTI)<\/strong>. Pre-silicon simulation did not flag the floating-node case due to the initial conditions the simulator applies, preventing the very condition responsible. Final test could not screen for the effect because the resulting offset is sub-microvolt at t = 0<\/strong> and accumulates only after days of biased operation.\n<\/p>\n\n

\nThis case study underscores the importance of integrating aging-aware design verification with adaptive test strategies for analog devices intended for long-deployment applications. The presentation walks through the diagnostic flow, the validated workaround shipped to the customer during silicon respin development, and the design corrections incorporated in successor revisions. We conclude with recommendations for screening long-latency, bias-dependent drift in the analog devices on which AI and HPC test programs increasingly depend, including SOA analysis<\/strong> during pre-silicon verification, extended-stress characterization protocols<\/strong>, and closer coordination between design verification and production test engineering teams.\n<\/p><\/p>

Hailin is an Applications Engineer at ElevATE Semiconductor with a strong engineering background and a passion for innovation. He holds a degree from the University of Toronto, where he also engaged in academic research collaborations, and has professional experience spanning software development and mixed-signal engineering.<\/p>\n\n

Dedicated to tackling complex technical challenges and fostering opportunities for students, Hailin is committed to advancing the field of semiconductor test while inspiring the next generation of professionals. He is currently pursuing a master\u2019s degree at UC Berkeley, focusing on applying statistical models and data science principles to enhance test engineering.<\/p><\/p><\/details>\n

\n\t\ucd08\ub85d - \uc804\uae30 (Korean)<\/summary>\n

Silent Data Corruption(SDC) \ubc0f \uc2e4\uc81c \uc2dc\uc2a4\ud15c \ubc30\ud3ec \uc774\ud6c4 \ubc1c\uc0dd\ud558\ub294 \ud558\ub4dc\uc6e8\uc5b4 \uacb0\ud568(Post-Deployment Hardware Fault)\uc740 \ucd5c\uadfc \ud558\uc774\ud37c\uc2a4\ucf00\uc77c AI \ubc0f HPC \uc778\ud504\ub77c\uc5d0\uc11c \uc911\uc694\ud55c \uc2e0\ub8b0\uc131 \ubb38\uc81c\ub85c \ub300\ub450\ub418\uace0 \uc788\uc2b5\ub2c8\ub2e4. Google, Meta \ubc0f OCP\uc758 \ucd5c\uadfc \uc0b0\uc5c5 \ubcf4\uace0\uc5d0\uc11c\ub3c4 \uc81c\uc870 \ud14c\uc2a4\ud2b8\ub97c \ud1b5\uacfc\ud588\uc9c0\ub9cc \ud2b9\uc815 Bias\uc870\uac74\uc774\ub098 \uc7a5\uc2dc\uac04 \ub3d9\uc791 \uc774\ud6c4\uc5d0\ub9cc \ub098\ud0c0\ub098\ub294 \uacb0\ud568 \uc0ac\ub840\ub4e4\uc774 \ubcf4\uace0\ub418\uace0 \uc788\uc2b5\ub2c8\ub2e4. \uae30\uc874\uc5d0 \ubc1c\ud45c\ub41c \uc0ac\ub840\ub4e4\uc740 \ub300\ubd80\ubd84 \ub514\uc9c0\ud138 \ud68c\ub85c\uc5d0 \uc9d1\uc911\ub418\uc5b4 \uc788\uc2b5\ub2c8\ub2e4. \ubcf8 \uc5f0\uad6c\uc5d0\uc11c\ub294 \ub3d9\uc77c\ud55c \uc720\ud615\uc758 \uace0\uc7a5 \uba54\ucee4\ub2c8\uc998\uc744 AI \ubc0f HPC\ubc18\ub3c4\uccb4\uc758 Final Test\uc5d0 \uc0ac\uc6a9\ub418\ub294 Analog ATE Pin Electronics ASIC\uc5d0\uc11c \ubd84\uc11d\ud558\uc600\uc2b5\ub2c8\ub2e4.<\/p>\n\n

\uace0\uac1d\uc740 256\ucc44\ub110 \uc560\ud50c\ub9ac\ucf00\uc774\uc158\uc5d0\uc11c \uc810\uc9c4\uc801\uc778 VCOM Threshold Drift\uac00 \ubc1c\uc0dd\ud55c\ub2e4\uace0 \ubcf4\uace0\ud558\uc600\uc2b5\ub2c8\ub2e4. \uc774 \ud604\uc0c1\uc740 \uc804\uccb4 \ucc44\ub110\uc758 \uc57d 50%\uc5d0\uc11c \ub098\ud0c0\ub0ac\uc73c\uba70, VCOM Threshold\uac00 -900mV\ub97c \ub118\uc5b4\uc120 \uc774\ud6c4\uc5d0\ub3c4 \uc548\uc815\ud654\ub418\uc9c0 \uc54a\uace0 \uacc4\uc18d \ubcc0\ud654\ud558\uc600\uc2b5\ub2c8\ub2e4. \ubb38\uc81c\uac00 \ubc1c\uc0dd\ud55c \ubaa8\ub4e0 \ub514\ubc14\uc774\uc2a4\ub294 \uc591\uc0b0 \uc804 Final Test\ub97c \uc815\uc0c1\uc801\uc73c\ub85c \ud1b5\uacfc\ud55c \uc81c\ud488\uc774\uc5c8\uc2b5\ub2c8\ub2e4. \ubd88\ub7c9 \ub514\ubc14\uc774\uc2a4\uc5d0 \ub300\ud574 \ucd08\uae30 \uc721\uc548\uac80\uc0ac, ATE\uc7ac\uc2dc\ud5d8 \ubc0f Emission Microscopy\ub97c \uc2e4\uc2dc\ud588\uc9c0\ub9cc \uba85\ud655\ud55c \uc6d0\uc778\uc744 \ud655\uc778\ud560 \uc218 \uc5c6\uc5c8\uc2b5\ub2c8\ub2e4. \uc5ec\ub7ec Lot\uc640 Data Code\uc5d0 \uac78\uce5c 50\uac1c \ub514\ubc14\uc774\uc2a4\uc758 Bench Characterization\uc744 \ud1b5\ud574 \ud574\ub2f9 Drift\ud604\uc0c1\uc774 \uc7ac\ud604 \uac00\ub2a5\ud568\uc744 \ud655\uc778\ud558\uc600\uc73c\uba70, Register Configuration\uacfc Operating Temperature\uc5d0 \ud06c\uac8c \uc758\uc874\ud558\ub294 \uac83\uc73c\ub85c \ub098\ud0c0\ub0ac\uc2b5\ub2c8\ub2e4. \uadf8\ub7ec\ub098 \uc774 \ud604\uc0c1\uc740 \uc2dc\uac04\uc774 \uacbd\uacfc\ud558\uba74\uc11c \ub204\uc801\ub418\ub294 \ud2b9\uc131\uc744 \uac00\uc9c0\uace0 \uc788\uc5b4 \uc77c\ubc18\uc801\uc778 \uc591\uc0b0 \uc2a4\ud06c\ub9ac\ub2dd \uacfc\uc815\uc5d0\uc11c\ub294 \uac80\ucd9c\ub418\uc9c0 \uc54a\uc558\uc2b5\ub2c8\ub2e4.<\/p>\n\n

Focused Ion Beam(FIB)\uacfc \uac19\uc740 Failure Analysis(FA) \uae30\ubc95\uc740 \ucd08\uae30 \ubd84\uc11d \uacfc\uc815\uc5d0\uc11c \uc624\ud574\ub97c \uc77c\uc73c\ud0ac \uc218 \uc788\ub294 \uacb0\uacfc\ub97c \ubcf4\uc5ec\uc8fc\uc5c8\uc2b5\ub2c8\ub2e4. Comparator \uacbd\ub85c\uc758 Capacitor\uc640 Diode\ub97c FIB\ub85c \uc808\ub2e8\ud558\uc790 Drift\uac00 \uba48\ucd94\uc5c8\uace0, \ucc98\uc74c\uc5d0\ub294 \ud574\ub2f9 \ubd80\ud488\ub4e4\uc774 \ubb38\uc81c\uc758 \uc6d0\uc778\uc778 \uac83\uc73c\ub85c \ud310\ub2e8\ub418\uc5c8\uc2b5\ub2c8\ub2e4. \uadf8\ub7ec\ub098 \uc774\ud6c4 \ud68c\ub85c \uae30\ub2a5\uacfc \ubb34\uad00\ud55c Metal\uc744 \uc808\ub2e8\ud558\ub294 Control FIB \uc2e4\ud5d8\uc5d0\uc11c\ub3c4 Drift\uac00 \uba48\ucd94\ub294 \ud604\uc0c1\uc774 \ud655\uc778\ub418\uc5c8\uc2b5\ub2c8\ub2e4. \uc774\ub294 \ud2b9\uc815 \uc18c\uc790\uac00 \uc6d0\uc778\uc774\uc5c8\ub358 \uac83\uc774 \uc544\ub2c8\ub77c FIB \uacf5\uc815 \uc790\uccb4\uac00 \uce21\uc815 \ub300\uc0c1\uc5d0 \uc601\ud5a5\uc744 \uc8fc\uc5b4 \ud604\uc0c1\uc744 \ubcc0\ud654\uc2dc\ud0a4\uace0 \uc788\uc5c8\uc74c\uc744 \uc758\ubbf8\ud569\ub2c8\ub2e4. \uc774\ub7ec\ud55c \uce68\uc2b5\uc801 \ubd84\uc11d(Invasive Characterization)\uc5d0 \ub300\ud55c \ubbfc\uac10\uc131\uc740 \uc774\uc640 \uac19\uc740 \uacb0\ud568\uc744 \ubd84\uc11d\ud560 \ub54c \uc8fc\uc758\ud574\uc57c \ud560 \uc911\uc694\ud55c \uc694\uc18c\uc774\uba70, \uc774\ud6c4 Debug Experiment\uc758 \uc124\uacc4\uc5d0\ub3c4 \uc81c\uc57d\uc744 \uc904 \uc218 \uc788\uc2b5\ub2c8\ub2e4.<\/p>\n\n

\ucd5c\uc885\uc801\uc73c\ub85c \uadfc\ubcf8 \uc6d0\uc778\uc740 Analog Comparator \ub0b4\ubd80\uc758 Safe Operating Area(SOA) \uc704\ubc18\uc73c\ub85c \ubc1d\ud600\uc84c\uc2b5\ub2c8\ub2e4. \ud2b9\uc815 Register State\uc5d0\uc11c \ubc1c\uc0dd\ud558\ub294 Floating-Node Condition\uacfc \ub610 \ub2e4\ub978 \uc0c1\ud0dc\uc5d0\uc11c Gain Stage\uc758 Vgs\uac00 \uacfc\ub3c4\ud55c Stress\ub97c \ubc1b\ub294 \ud604\uc0c1\uc73c\ub85c \uc778\ud574 Gate Oxide\uac00 \uc9c0\uc18d\uc801\uc778 Overstress\uc5d0 \ub178\ucd9c\ub418\uc5c8\uc73c\uba70, \uadf8 \uacb0\uacfc Hot Carrier Injection(HCI) \ubc0f Bias Temperature Instability(BTI)\uac00 \uac00\uc18d\ub418\uc5c8\uc2b5\ub2c8\ub2e4. Pre-Silicon Simulation\uc5d0\uc11c\ub294 Simulator\uac00 \uc801\uc6a9\ud558\ub294 Initial Condition\uc73c\ub85c \uc778\ud574 \uc2e4\uc81c \ubb38\uc81c\ub97c \uc720\ubc1c\ud558\ub294 Floating-Node Condition \uc790\uccb4\uac00 \ubc1c\uc0dd\ud558\uc9c0 \uc54a\uc544 \ud574\ub2f9 \ubb38\uc81c\ub97c \uc0ac\uc804\uc5d0 \uac80\ucd9c\ud558\uc9c0 \ubabb\ud588\uc2b5\ub2c8\ub2e4. \ub610\ud55c Final Test \uc2dc\uc810(t=0)\uc5d0\uc11c \ubc1c\uc0dd\ud558\ub294 Offset\uc740 Sub-Microvolt \uc218\uc900\uc73c\ub85c \ub9e4\uc6b0 \uc791\uace0, Bias\uac00 \uc778\uac00\ub41c \uc0c1\ud0dc\uc5d0\uc11c \uc218\uc77c\uac04 \ub3d9\uc791\ud55c \uc774\ud6c4\uc5d0\uc57c \ub204\uc801\ub418\uc5b4 \ub098\ud0c0\ub098\uae30 \ub54c\ubb38\uc5d0 \uc77c\ubc18\uc801\uc778 Final Test\ub85c\ub294 Screening\ud558\uae30 \uc5b4\ub824\uc6e0\uc2b5\ub2c8\ub2e4.<\/p>\n\n

\ubcf8 \uc0ac\ub840\ub294 \uc7a5\uae30\uac04 \uc0ac\uc6a9\ub418\ub294 Analog Device\uc758 \uc2e0\ub8b0\uc131\uc744 \ud655\ubcf4\ud558\uae30 \uc704\ud574 Aging-Aware Design Verification\uacfc Adaptive Test Strategy\ub97c \ud1b5\ud569\ud558\ub294 \uac83\uc774 \uc911\uc694\ud568\uc744 \ubcf4\uc5ec\uc90d\ub2c8\ub2e4. \ubcf8 \ubc1c\ud45c\uc5d0\uc11c\ub294 \ubb38\uc81c\uc758 Diagnostic Flow, Silicon Respin \uac1c\ubc1c \uae30\uac04 \ub3d9\uc548 \uace0\uac1d\uc5d0\uac8c \uc81c\uacf5\ud558\uc5ec \uac80\uc99d\ub41c Workaround, \uadf8\ub9ac\uace0 \ud6c4\uc18d Revision\uc5d0 \uc801\uc6a9\ub41c Design Correction \uacfc\uc815\uc744 \ub2e8\uacc4\uc801\uc73c\ub85c \uc18c\uac1c\ud569\ub2c8\ub2e4. \ub9c8\uc9c0\ub9c9\uc73c\ub85c AI \ubc0f HPC Test Program\uc5d0\uc11c \uc911\uc694\uc131\uc774 \uc810\ucc28 \ub192\uc544\uc9c0\uace0 \uc788\ub294 Analog Device\uc758 \uc7a5\uae30 \uc7a0\ubcf5\ud615(Long-Latency), Bias-Dependent Drift\ub97c \ud6a8\uacfc\uc801\uc73c\ub85c \uac80\ucd9c\ud558\uae30 \uc704\ud55c \ubc29\uc548\uc744 \uc81c\uc548\ud569\ub2c8\ub2e4. \uc5ec\uae30\uc5d0\ub294 Pre-Silicon Verification \ub2e8\uacc4\uc5d0\uc11c\uc758 SOA Analysis, Extended-Stress Characterization Protocol, \uadf8\ub9ac\uace0 Design Verification Team\uacfc Production Test Engineering Team \uac04\uc758 \ubcf4\ub2e4 \uae34\ubc00\ud55c \ud611\uc5c5\uc774 \ud3ec\ud568\ub429\ub2c8\ub2e4.<\/p>\n<\/p>

Hailin<\/strong>\uc740 ElevATE Semiconductor<\/strong>\uc758 Applications Engineer<\/strong>\ub85c, \ud0c4\ud0c4\ud55c \uc5d4\uc9c0\ub2c8\uc5b4\ub9c1 \uae30\ubc18\uacfc \uae30\uc220 \ud601\uc2e0\uc5d0 \ub300\ud55c \ub192\uc740 \uad00\uc2ec\uc744 \ubc14\ud0d5\uc73c\ub85c \ubc18\ub3c4\uccb4 \ud14c\uc2a4\ud2b8 \ubd84\uc57c\uc5d0\uc11c \ud65c\ub3d9\ud558\uace0 \uc788\uc2b5\ub2c8\ub2e4. \uadf8\ub294 University of Toronto<\/strong>\uc5d0\uc11c \ud559\uc704\ub97c \ucde8\ub4dd\ud588\uc73c\uba70, \uc7ac\ud559 \uc911 Academic Research Collaboration<\/strong>\uc5d0\ub3c4 \ucc38\uc5ec\ud558\uc600\uc2b5\ub2c8\ub2e4. \ub610\ud55c Software Development<\/strong> \ubc0f Mixed-Signal Engineering<\/strong> \ubd84\uc57c\uc5d0\uc11c \ub2e4\uc591\ud55c \uc2e4\ubb34 \uacbd\ud5d8\uc744 \ubcf4\uc720\ud558\uace0 \uc788\uc2b5\ub2c8\ub2e4.<\/p>\n\n

Hailin\uc740 \ubcf5\uc7a1\ud55c \uae30\uc220\uc801 \ubb38\uc81c\ub97c \ud574\uacb0\ud558\ub294 \ub3d9\uc2dc\uc5d0 \ud559\uc0dd\ub4e4\uc5d0\uac8c \uc0c8\ub85c\uc6b4 \uae30\ud68c\ub97c \uc81c\uacf5\ud558\ub294 \ub370\uc5d0\ub3c4 \uad00\uc2ec\uc744 \uac00\uc9c0\uace0 \uc788\uc73c\uba70, Semiconductor Test<\/strong> \uae30\uc220\uc758 \ubc1c\uc804\uacfc \ucc28\uc138\ub300 \uc804\ubb38 \uc778\ub825 \uc591\uc131\uc5d0 \uae30\uc5ec\ud558\uace0\uc790 \ub178\ub825\ud558\uace0 \uc788\uc2b5\ub2c8\ub2e4. \ud604\uc7ac UC Berkeley<\/strong>\uc5d0\uc11c \uc11d\uc0ac\uacfc\uc815\uc744 \uc774\uc218 \uc911\uc774\uba70, Statistical Models<\/strong>\uc640 Data Science<\/strong> \uc6d0\ub9ac\ub97c Test Engineering<\/strong>\uc5d0 \uc801\uc6a9\ud558\uc5ec \ud14c\uc2a4\ud2b8 \uae30\uc220\uacfc \uc131\ub2a5\uc744 \ud5a5\uc0c1\uc2dc\ud0a4\ub294 \uc5f0\uad6c\uc5d0 \uc9d1\uc911\ud558\uace0 \uc788\uc2b5\ub2c8\ub2e4.<\/p>\n<\/p><\/details>\n<\/div>\n

\n
\n“From Test Floor to Thinking Floor: The Agentic Future of Silicon Test” \n
“\ud14c\uc2a4\ud2b8 \ud50c\ub85c\uc5b4\uc5d0\uc11c \uc53d\ud0b9 \ud50c\ub85c\uc5b4\ub85c: \ubc18\ub3c4\uccb4 \ud14c\uc2a4\ud2b8\uc758 \uc5d0\uc774\uc804\ud2b8 \uae30\ubc18 \ubbf8\ub798” \n<\/div>\n
\n
\n
\nMykola Zakharchuk\n <\/div>\n\t
\nAdvantest\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract - Biography (English)<\/summary>\n

Abstract<\/h3>\n\n

\nSemiconductor test today operates as a sequence of disconnected stages \u2014 EDA, wafer sort, final test,\nsystem-level test, reliability, and field \u2014 each with its own tools, its own datalog format, and its own engineering\nteams. The result is well understood across the industry: an SLT escape rarely traces cleanly back to a sort\nsignature, characterization data is reconstructed by hand for every yield investigation, and the engineer's most\nexpensive task is not running tests but stitching context together across stages.\n<\/p>\n\n

\nThis talk proposes a different shape for the next decade of test: a thinking test floor in which the tester becomes\na deterministic execution engine, the IDE becomes optional, and a fleet of discipline-specialized AI agents \u2014\nTest, Thermal, Characterization, Yield, Reliability, SLT, Application Engineering \u2014 operates above a unified\nanalytics platform on a common Device Log that follows each die from EDA through field return.\n<\/p>\n\n

\nWe will outline a vendor-neutral, three-layer architecture that makes this possible:\n<\/p>\n\n

    \n
  1. \n An Agent Fleet<\/strong> the engineer steers at the level of intent rather than clicks.\n <\/li>\n
  2. \n An Agentic Control Plane<\/strong> that translates intent into measurement operations through\n domain-shaped tools and enforces hardware-safety envelopes structurally.\n <\/li>\n
  3. \n A headless execution layer<\/strong> with a stable contract for ingesting machine-authored,\n signed, version-controlled test programs.\n <\/li>\n<\/ol>\n\n

    \nBinding the three layers together is a Unified Device Log<\/strong> \u2014 a schemaed, append-only,\ncustomer-owned record keyed to each device's lifelong identity \u2014 which turns cross-stage investigation from a\nproject into a query.\n<\/p>\n\n

    \nWe will also examine the corresponding shift toward simulation-led test development, in which agents iterate\nagainst virtual testers and digital-twin device models long before silicon is touched, and discuss what this means\nfor tooling, IP boundaries, customer trust, and the engineering organizations that operate the test floor.\n<\/p>\n\n

    What Attendees Will Take Away<\/h3>\n\n
      \n
    • \n A concrete architectural picture of how AI agents move from \"smarter autocomplete inside the IDE\" to\n first-class operators of the test floor across every stage from EDA to SLT.\n <\/li>\n
    • \n A practical framing of the Unified Device Log as the spine that makes cross-stage investigation tractable \u2014\n including schema, identity propagation, and the customer IP boundary.\n <\/li>\n
    • \n A clear distinction between an agent that has hands (action surface), knowledge (domain-shaped tools), and\n memory (the device log) \u2014 and why all three are required for autonomy.\n <\/li>\n
    • \n Why simulation and digital-twin-led development is the natural next step once test programs become\n machine-authored artifacts rather than hand-edited files.\n <\/li>\n
    • \n An honest discussion of the open problems: hardware safety on live silicon, customer-IP protection,\n agent guardrails, and the organizational changes that come with intent-driven testing.\n <\/li>\n<\/ul>\n\n

      Audience and Relevance<\/h3>\n\n

      \nTest engineers, characterization engineers, yield and reliability leads, ATE platform architects, EDA and SLT\npractitioners, and engineering and executive leadership looking to catch the next stage of the semiconductor\ntest era.\n<\/p>\n\n

      \nParticularly relevant for organizations facing the cost of cross-stage data fragmentation and looking for a\ncredible path from today's IDE-centric workflows to AI-native, intent-driven test operations.\n<\/p><\/p>

      \nMykola Zakharchuk<\/strong> is Product Owner at Advantest with ten years of experience in semiconductor test.\nHe works at the intersection of generative AI and automated test, focusing on how large language models,\nagent frameworks, and open protocols such as the Model Context Protocol are reshaping the way test\nprograms are authored, executed, and debugged.\n<\/p>\n\n

      \nHis current work centers on the long-term vision for an agentic test platform spanning EDA through SLT,\nwith a common analytics layer and a Unified Device Log as its spine. He speaks regularly on the future of AI\nin semiconductor test.\n<\/p><\/p><\/details>\n

      \n\t\ucd08\ub85d - \uc804\uae30 (Korean)<\/summary>\n

      \ucd08\ub85d<\/h3>\n\n

      \n\uc624\ub298\ub0a0 \ubc18\ub3c4\uccb4 \ud14c\uc2a4\ud2b8\ub294 EDA, \uc6e8\uc774\ud37c \uc18c\ud2b8, \ud30c\uc774\ub110 \ud14c\uc2a4\ud2b8, \uc2dc\uc2a4\ud15c \ub808\ubca8 \ud14c\uc2a4\ud2b8(SLT), \uc2e0\ub8b0\uc131,\n\ud544\ub4dc\uc5d0 \uc774\ub974\uae30\uae4c\uc9c0 \uc11c\ub85c \ub2e8\uc808\ub41c \ub2e8\uacc4\ub4e4\uc758 \uc5f0\uc18d\uc73c\ub85c \uc6b4\uc601\ub418\uba70, \uac01 \ub2e8\uacc4\ub294 \uace0\uc720\uc758 \ud234\uacfc \ub370\uc774\ud130\ub85c\uadf8\n\ud3ec\ub9f7, \uadf8\ub9ac\uace0 \ubcc4\ub3c4\uc758 \uc5d4\uc9c0\ub2c8\uc5b4\ub9c1 \ud300\uc744 \uac00\uc9c0\uace0 \uc788\uc2b5\ub2c8\ub2e4.\n<\/p>\n\n

      \n\uadf8 \uacb0\uacfc\ub294 \uc5c5\uacc4\uc5d0 \uc798 \uc54c\ub824\uc838 \uc788\uc2b5\ub2c8\ub2e4. SLT \ub2e8\uacc4\uc758 \ubd88\ub7c9(escape)\uc774 \uc18c\ud2b8 \uc2dc\uadf8\ub2c8\ucc98\ub85c \uae54\ub054\ud558\uac8c\n\ucd94\uc801\ub418\ub294 \uacbd\uc6b0\ub294 \ub4dc\ubb3c\uace0, \ud2b9\uc131\ud654(characterization) \ub370\uc774\ud130\ub294 \uc218\uc728 \ubd84\uc11d\ub9c8\ub2e4 \uc218\uc791\uc5c5\uc73c\ub85c \uc7ac\uad6c\uc131\ub418\uba70,\n\uc5d4\uc9c0\ub2c8\uc5b4\uc758 \uac00\uc7a5 \uac12\ube44\uc2fc \uc5c5\ubb34\ub294 \ud14c\uc2a4\ud2b8 \uc2e4\ud589 \uc790\uccb4\uac00 \uc544\ub2c8\ub77c \uc5ec\ub7ec \ub2e8\uacc4\uc5d0 \uac78\uce5c \ubb38\ub9e5\uc744 \uc774\uc5b4 \ubd99\uc774\ub294\n\uc77c\uc785\ub2c8\ub2e4.\n<\/p>\n\n

      \n\ubcf8 \ubc1c\ud45c\ub294 \ud5a5\ud6c4 10\ub144\uc758 \ud14c\uc2a4\ud2b8\uc5d0 \ub300\ud574 \ub2e4\ub978 \ud615\ud0dc\ub97c \uc81c\uc548\ud569\ub2c8\ub2e4. \ud14c\uc2a4\ud130\ub294 \uacb0\uc815\ub860\uc801(deterministic)\n\uc2e4\ud589 \uc5d4\uc9c4\uc774 \ub418\uace0, IDE\ub294 \uc120\ud0dd \uc0ac\ud56d\uc774 \ub418\uba70, \ubd84\uc57c\ubcc4\ub85c \ud2b9\ud654\ub41c AI \uc5d0\uc774\uc804\ud2b8 \uc9d1\ub2e8 \u2014 \ud14c\uc2a4\ud2b8,\n\uc5f4(Thermal), \ud2b9\uc131\ud654, \uc218\uc728, \uc2e0\ub8b0\uc131, SLT, \uc560\ud50c\ub9ac\ucf00\uc774\uc158 \uc5d4\uc9c0\ub2c8\uc5b4\ub9c1 \u2014 \uc774 \ud1b5\ud569 \ubd84\uc11d \ud50c\ub7ab\ud3fc \uc704\uc5d0\uc11c,\nEDA\ubd80\ud130 \ud544\ub4dc \ubc18\ud488\uae4c\uc9c0 \uac01 \ub2e4\uc774(die)\ub97c \ub530\ub77c\ub2e4\ub2c8\ub294 \uacf5\ud1b5 \ub514\ubc14\uc774\uc2a4 \ub85c\uadf8(Device Log)\ub97c \uae30\ubc18\uc73c\ub85c\n\ub3d9\uc791\ud558\ub294 \u2018\uc0ac\uace0\ud558\ub294 \ud14c\uc2a4\ud2b8 \ud50c\ub85c\uc5b4(thinking test floor)\u2019\uc785\ub2c8\ub2e4.\n<\/p>\n\n

      \n\uc774\ub97c \uac00\ub2a5\ud558\uac8c \ud558\ub294 \ubca4\ub354 \uc911\ub9bd\uc801(vendor-neutral) 3\uacc4\uce35 \uc544\ud0a4\ud14d\ucc98\ub97c \uc18c\uac1c\ud569\ub2c8\ub2e4.\n<\/p>\n\n

        \n
      1. \n \uc5d4\uc9c0\ub2c8\uc5b4\uac00 \ud074\ub9ad\uc774 \uc544\ub2c8\ub77c \uc758\ub3c4(intent) \uc218\uc900\uc5d0\uc11c \uc870\uc885\ud558\ub294 \uc5d0\uc774\uc804\ud2b8 \ud50c\ub9bf(Agent Fleet)<\/strong>.\n <\/li>\n
      2. \n \uc758\ub3c4\ub97c \ub3c4\uba54\uc778\uc5d0 \ub9de\ucdb0\uc9c4 \ud234\uc744 \ud1b5\ud574 \uce21\uc815 \ub3d9\uc791\uc73c\ub85c \ubcc0\ud658\ud558\uace0 \ud558\ub4dc\uc6e8\uc5b4 \uc548\uc804 \ubc94\uc704(safety envelope)\ub97c\n \uad6c\uc870\uc801\uc73c\ub85c \uac15\uc81c\ud558\ub294 \uc5d0\uc774\uc804\ud2f1 \ucee8\ud2b8\ub864 \ud50c\ub808\uc778(Agentic Control Plane)<\/strong>.\n <\/li>\n
      3. \n \uae30\uacc4\uac00 \uc791\uc131\ud558\uace0 \uc11c\uba85\u00b7\ubc84\uc804 \uad00\ub9ac\ub41c \ud14c\uc2a4\ud2b8 \ud504\ub85c\uadf8\ub7a8\uc744 \uc218\uc6a9\ud558\ub294 \uc548\uc815\uc801 \uacc4\uc57d(contract)\uc744 \uac16\ucd98\n \ud5e4\ub4dc\ub9ac\uc2a4(headless) \uc2e4\ud589 \uacc4\uce35<\/strong>.\n <\/li>\n<\/ol>\n\n

        \n\uc774 \uc138 \uacc4\uce35\uc744 \ud558\ub098\ub85c \ubb36\ub294 \uac83\uc740 \ud1b5\ud569 \ub514\ubc14\uc774\uc2a4 \ub85c\uadf8(Unified Device Log)<\/strong>\ub85c,\n\uac01 \ub514\ubc14\uc774\uc2a4\uc758 \ud3c9\uc0dd \uc2dd\ubcc4\uc790\uc5d0 \uc5f0\uacb0\ub41c \uc2a4\ud0a4\ub9c8 \uae30\ubc18\uc758 \ucd94\uac00 \uc804\uc6a9(append-only)\u00b7\uace0\uac1d \uc18c\uc720 \uae30\ub85d\uc774\uba70,\n\ub2e8\uacc4 \uac04 \ubd84\uc11d\uc744 \ud558\ub098\uc758 \ud504\ub85c\uc81d\ud2b8\uc5d0\uc11c \ud558\ub098\uc758 \ucffc\ub9ac\ub85c \ubc14\uafd4 \ub193\uc2b5\ub2c8\ub2e4.\n<\/p>\n\n

        \n\ub610\ud55c \uc2e4\uc81c \uc2e4\ub9ac\ucf58\uc744 \ub2e4\ub8e8\uae30 \ud6e8\uc52c \uc804\uc5d0 \uc5d0\uc774\uc804\ud2b8\uac00 \uac00\uc0c1 \ud14c\uc2a4\ud130\uc640 \ub514\uc9c0\ud138 \ud2b8\uc708 \ub514\ubc14\uc774\uc2a4 \ubaa8\ub378\uc744\n\ub300\uc0c1\uc73c\ub85c \ubc18\ubcf5 \uac1c\ubc1c\uc744 \uc218\ud589\ud558\ub294 \uc2dc\ubbac\ub808\uc774\uc158 \uc8fc\ub3c4(simulation-led) \ud14c\uc2a4\ud2b8 \uac1c\ubc1c\ub85c\uc758 \uc804\ud658\uc744 \uc0b4\ud3b4\ubcf4\uace0,\n\uc774\uac83\uc774 \ud234\ub9c1, IP \uacbd\uacc4, \uace0\uac1d \uc2e0\ub8b0, \uadf8\ub9ac\uace0 \ud14c\uc2a4\ud2b8 \ud50c\ub85c\uc5b4\ub97c \uc6b4\uc601\ud558\ub294 \uc5d4\uc9c0\ub2c8\uc5b4\ub9c1 \uc870\uc9c1\uc5d0 \uc5b4\ub5a4 \uc758\ubbf8\ub97c\n\uac16\ub294\uc9c0 \ub17c\uc758\ud569\ub2c8\ub2e4.\n<\/p><\/p>

        \n\ubbf8\ucf5c\ub77c \uc790\ud558\ub974\ucd94\ud06c(Mykola Zakharchuk)<\/strong>\ub294 Advantest\uc758 \ud504\ub85c\ub355\ud2b8 \uc624\ub108(Product Owner)\ub85c,\n\ubc18\ub3c4\uccb4 \ud14c\uc2a4\ud2b8 \ubd84\uc57c\uc5d0\uc11c 10\ub144\uc758 \uacbd\ub825\uc744 \ubcf4\uc720\ud558\uace0 \uc788\uc2b5\ub2c8\ub2e4.\n<\/p>\n\n

        \n\uadf8\ub294 \uc0dd\uc131\ud615 AI\uc640 \uc790\ub3d9 \ud14c\uc2a4\ud2b8\uc758 \uc811\uc810\uc5d0\uc11c, \ub300\uaddc\ubaa8 \uc5b8\uc5b4 \ubaa8\ub378(LLM), \uc5d0\uc774\uc804\ud2b8 \ud504\ub808\uc784\uc6cc\ud06c,\n\uadf8\ub9ac\uace0 Model Context Protocol\uacfc \uac19\uc740 \uac1c\ubc29\ud615 \ud504\ub85c\ud1a0\ucf5c\uc774 \ud14c\uc2a4\ud2b8 \ud504\ub85c\uadf8\ub7a8\uc758 \uc791\uc131\u00b7\uc2e4\ud589\u00b7\ub514\ubc84\uae45\n\ubc29\uc2dd\uc744 \uc5b4\ub5bb\uac8c \ubcc0\ud654\uc2dc\ud0a4\uace0 \uc788\ub294\uc9c0\uc5d0 \uc8fc\ubaa9\ud558\uba70 \uc5f0\uad6c\ud558\uace0 \uc788\uc2b5\ub2c8\ub2e4.\n<\/p>\n\n

        \n\ud604\uc7ac\ub294 EDA\ubd80\ud130 SLT\uae4c\uc9c0 \uc544\uc6b0\ub974\ub294 \uc5d0\uc774\uc804\ud2b8 \uae30\ubc18 \ud14c\uc2a4\ud2b8 \ud50c\ub7ab\ud3fc\uacfc, \uadf8 \uc911\uc2ec\ucd95\uc774 \ub418\ub294 \uacf5\ud1b5 \ubd84\uc11d\n\uacc4\uce35 \ubc0f \ud1b5\ud569 \ub514\ubc14\uc774\uc2a4 \ub85c\uadf8(Unified Device Log)\uc5d0 \ub300\ud55c \uc7a5\uae30 \ube44\uc804\uc5d0 \uc9d1\uc911\ud558\uace0 \uc788\uc2b5\ub2c8\ub2e4.\n<\/p>\n\n

        \n\uadf8\ub294 \ubc18\ub3c4\uccb4 \ud14c\uc2a4\ud2b8 \ubd84\uc57c\uc5d0\uc11c AI\uc758 \ubbf8\ub798\uc5d0 \ub300\ud574 \uc815\uae30\uc801\uc73c\ub85c \uac15\uc5f0\ud558\uace0 \uc788\uc2b5\ub2c8\ub2e4.\n<\/p><\/p><\/details>\n<\/div>\n

        \n
        \n“A HW or SW approach to Power Supply Rail Multi Switching on a Device Power Supply (DPS)” \n
        “Device Power Supply(DPS)\uc758 Power Supply Rail Multi Switching\uc744 \uc704\ud55c HW\/SW \uc811\uadfc \ubc29\uc2dd” \n<\/div>\n
        \n
        \n
        \nThomas Angelo C. Abiog\n <\/div>\n\t
        \nElevATE Semiconductor\n\t <\/div>\n <\/div>\n<\/div>\n
        \n\tAbstract - Biography (English)<\/summary>\n

        \nThis paper presents a hardware (HW)<\/strong> and software (SW)<\/strong> approach to Power Supply Rail Multi Switching<\/strong> on a Device Power Supply (DPS)<\/strong> using multiple voltage rails. Implemented with the Whitney DPS<\/strong> as a demonstration platform, the system selects the most efficient voltage rail based on output demand to reduce power loss, lower heat dissipation, and improve thermal performance. The design supports both hardware-based comparator logic<\/strong> and software-based digital control<\/strong> for flexible envelope-tracking operation.\n<\/p>\n\n

        \nThe solution uses make-before-break rail switching<\/strong>, eFuse protection<\/strong>, buffered voltage sensing<\/strong>, and threshold-based control<\/strong> to maintain continuous operation during voltage transitions. Results from both hardware and software demonstrations at 200 mA<\/strong>, 500 mA<\/strong>, and up to 1 A<\/strong> show stable rail handoff and reliable output regulation across changing load conditions.\n<\/p>\n\n

        \nThese results demonstrate that the proposed Envelope-Tracking Power Supply (ETPS)<\/strong> is an effective solution for improving power efficiency<\/em>, thermal management<\/em>, and system reliability<\/em> in high-voltage DPS applications.\n<\/p><\/p>

        Thomas Angelo C. Abiog<\/strong> is a Senior Product Applications Engineer at ElevATE Semiconductor<\/strong>, where he has contributed to the development and customer adoption of advanced semiconductor solutions for the past two years. He brings more than 11 years of experience in the Automated Test Equipment (ATE) industry, including an extensive tenure at Analog Devices, Inc.<\/strong>, where he served as a Product Applications Manager.<\/p>\n\n

        His technical expertise spans pin electronics, device power supplies, and ATE system applications. Throughout his career, Thomas has focused on translating customer requirements and real-world application challenges into practical engineering solutions, helping guide the development of next-generation ATE technologies.<\/p>\n\n

        Thomas is passionate about semiconductor innovation and remains actively engaged in advancing high-performance solutions for an evolving test and measurement industry. Outside of work, he enjoys playing badminton and exploring the cultural history, traditions, and stories of the locations he visits.<\/p><\/p><\/details>\n

        \n\t\ucd08\ub85d - \uc804\uae30 (Korean)<\/summary>\n

        \ubcf8 \ub17c\ubb38\uc5d0\uc11c\ub294 \ub2e4\uc911 \uc804\uc555 \ub808\uc77c(Multiple Voltage Rails)\uc744 \uc0ac\uc6a9\ud558\ub294 Device Power Supply(DPS)\uc5d0\uc11c Power Supply Rail Multi Switching\uc744 \uad6c\ud604\ud558\uae30 \uc704\ud55c \ud558\ub4dc\uc6e8\uc5b4(HW) \ubc0f \uc18c\ud504\ud2b8\uc6e8\uc5b4(SW) \uc811\uadfc \ubc29\uc2dd\uc744 \uc81c\uc2dc\ud569\ub2c8\ub2e4. \ubcf8 \uc2dc\uc2a4\ud15c\uc740 Whitney DPS\ub97c \ub370\ubaa8 \ud50c\ub7ab\ud3fc\uc73c\ub85c \uad6c\ud604\ud558\uc600\uc73c\uba70, \ucd9c\ub825 \uc694\uad6c \uc870\uac74(Output Demand)\uc5d0 \ub530\ub77c \uac00\uc7a5 \ud6a8\uc728\uc801\uc778 \uc804\uc555 \ub808\uc77c\uc744 \uc120\ud0dd\ud568\uc73c\ub85c\uc368 \uc804\ub825 \uc190\uc2e4\uc744 \uc904\uc774\uace0, \ubc1c\uc5f4\uc744 \uac10\uc18c\uc2dc\ud0a4\uba70, \uc5f4 \uc131\ub2a5(Thermal Performance)\uc744 \ud5a5\uc0c1\uc2dc\ud0a4\ub3c4\ub85d \uc124\uacc4\ub418\uc5c8\uc2b5\ub2c8\ub2e4. \ub610\ud55c \uc720\uc5f0\ud55c Envelope-Tracking \ub3d9\uc791\uc744 \uc704\ud574 \ud558\ub4dc\uc6e8\uc5b4 \uae30\ubc18 Comparator Logic\uacfc \uc18c\ud504\ud2b8\uc6e8\uc5b4 \uae30\ubc18 Digital Control \ubc29\uc2dd\uc744 \ubaa8\ub450 \uc9c0\uc6d0\ud569\ub2c8\ub2e4.<\/p>\n\n

        \ubcf8 \uc194\ub8e8\uc158\uc740 \uc804\uc555 \uc804\ud658 \uacfc\uc815\uc5d0\uc11c\ub3c4 \uc5f0\uc18d\uc801\uc778 \ub3d9\uc791\uc744 \uc720\uc9c0\ud558\uae30 \uc704\ud574 Make-Before-Break Rail Switching, eFuse Protection, Buffered Voltage Sensing, Threshold-Based Control \uae30\uc220\uc744 \uc801\uc6a9\ud558\uc600\uc2b5\ub2c8\ub2e4. \ud558\ub4dc\uc6e8\uc5b4 \ubc0f \uc18c\ud504\ud2b8\uc6e8\uc5b4 \ubc29\uc2dd\uc73c\ub85c \uac01\uac01 \uc218\ud589\ud55c 200 mA, 500 mA \ubc0f \ucd5c\ub300 1 A\uc758 \ub370\ubaa8 \ud14c\uc2a4\ud2b8 \uacb0\uacfc, \ubd80\ud558 \uc870\uac74\uc774 \ubcc0\ud654\ud558\ub294 \uc0c1\ud669\uc5d0\uc11c\ub3c4 \uc548\uc815\uc801\uc778 \uc804\uc555 \ub808\uc77c \uc804\ud658(Rail Handoff)\uacfc \uc2e0\ub8b0\uc131 \uc788\ub294 \ucd9c\ub825 \uc804\uc555 \uc81c\uc5b4(Output Regulation)\uac00 \uac00\ub2a5\ud568\uc744 \ud655\uc778\ud558\uc600\uc2b5\ub2c8\ub2e4.<\/p>\n\n

        \uc774\ub7ec\ud55c \uacb0\uacfc\ub294 \uc81c\uc548\ub41c Envelope-Tracking Power Supply(ETPS) \uae30\uc220\uc774 \uace0\uc804\uc555 DPS \uc560\ud50c\ub9ac\ucf00\uc774\uc158\uc5d0\uc11c \uc804\ub825 \ud6a8\uc728(Power Efficiency), \uc5f4 \uad00\ub9ac(Thermal Management) \ubc0f \uc2dc\uc2a4\ud15c \uc2e0\ub8b0\uc131(System Reliability)\uc744 \ud5a5\uc0c1\uc2dc\ud0a4\ub294 \ud6a8\uacfc\uc801\uc778 \uc194\ub8e8\uc158\uc784\uc744 \ubcf4\uc5ec\uc90d\ub2c8\ub2e4.<\/p>\n<\/p>

        Thomas Angelo C. Abiog<\/strong>\ub294 ElevATE Semiconductor<\/strong>\uc758 Senior Product Applications Engineer<\/strong>\ub85c, \uc9c0\ub09c 2\ub144\uac04 \ucca8\ub2e8 \ubc18\ub3c4\uccb4 \uc194\ub8e8\uc158\uc758 \uac1c\ubc1c \ubc0f \uace0\uac1d \uc801\uc6a9 \ud655\ub300\uc5d0 \uae30\uc5ec\ud574 \uc654\uc2b5\ub2c8\ub2e4. \uadf8\ub294 Automated Test Equipment (ATE)<\/strong> \uc0b0\uc5c5\uc5d0\uc11c 11\ub144 \uc774\uc0c1\uc758 \uacbd\ub825\uc744 \ubcf4\uc720\ud558\uace0 \uc788\uc73c\uba70, Analog Devices, Inc.<\/strong>\uc5d0\uc11c \uc624\ub79c \uae30\uac04 \uadfc\ubb34\ud558\uba70 Product Applications Manager<\/strong>\ub97c \uc5ed\uc784\ud588\uc2b5\ub2c8\ub2e4.<\/p>\n\n

        Thomas\uc758 \uc8fc\uc694 \uae30\uc220 \uc804\ubb38 \ubd84\uc57c\ub294 Pin Electronics<\/strong>, Device Power Supplies<\/strong> \ubc0f ATE System Applications<\/strong>\uc785\ub2c8\ub2e4. \uadf8\ub294 \ucee4\ub9ac\uc5b4 \uc804\ubc18\uc5d0 \uac78\uccd0 \uace0\uac1d\uc758 \uc694\uad6c\uc0ac\ud56d\uacfc \uc2e4\uc81c \uc560\ud50c\ub9ac\ucf00\uc774\uc158\uc5d0\uc11c \ubc1c\uc0dd\ud558\ub294 \uae30\uc220\uc801 \uacfc\uc81c\ub97c \uc2e4\uc6a9\uc801\uc778 \uc5d4\uc9c0\ub2c8\uc5b4\ub9c1 \uc194\ub8e8\uc158\uc73c\ub85c \uad6c\ud604\ud558\ub294 \ub370 \uc8fc\ub825\ud574 \uc654\uc73c\uba70, \uc774\ub97c \ud1b5\ud574 \ucc28\uc138\ub300 ATE<\/strong> \uae30\uc220 \uac1c\ubc1c\uc5d0 \uae30\uc5ec\ud574 \uc654\uc2b5\ub2c8\ub2e4.<\/p>\n\n

        Thomas\ub294 \ubc18\ub3c4\uccb4 \uae30\uc220 \ud601\uc2e0\uc5d0 \uae4a\uc740 \uad00\uc2ec\uc744 \uac00\uc9c0\uace0 \uc788\uc73c\uba70, \ube60\ub974\uac8c \ubcc0\ud654\ud558\ub294 Test & Measurement<\/strong> \uc0b0\uc5c5\uc744 \uc704\ud55c \uace0\uc131\ub2a5 \uc194\ub8e8\uc158 \uac1c\ubc1c\uc5d0 \uc9c0\uc18d\uc801\uc73c\ub85c \ucc38\uc5ec\ud558\uace0 \uc788\uc2b5\ub2c8\ub2e4. \uc5c5\ubb34 \uc678\uc5d0\ub294 \ubc30\ub4dc\ubbfc\ud134\uc744 \uc990\uae30\uba70, \ubc29\ubb38\ud558\ub294 \uc9c0\uc5ed\uc758 \ubb38\ud654\uc801 \uc5ed\uc0ac\uc640 \uc804\ud1b5, \uadf8\ub9ac\uace0 \uadf8 \uc9c0\uc5ed\uc5d0 \uc5bd\ud78c \uc774\uc57c\uae30\ub4e4\uc744 \ud0d0\uad6c\ud558\ub294 \uac83\uc744 \uc88b\uc544\ud569\ub2c8\ub2e4.<\/p>\n<\/p><\/details>\n<\/div>\n

        \n
        \n“Prober for Singulated Die Testing” \n
        “Singulated Die Test\ub97c \uc704\ud55c Prober” \n<\/div>\n
        \n
        \n
        \nSangyeong Han\n <\/div>\n\t
        \nSemics\n\t <\/div>\n <\/div>\n<\/div>\n
        \n\tAbstract - Biography (English)<\/summary>\n

        With the growth of AI and HPC applications, the use of HBM, chiplets, and other multi-die packages is increasing. As more dies are integrated into a single package, it becomes more important to verify the quality of each die before assembly. A defective die can result in the loss of other good dies and packaging components within the same package, increasing the importance of Known Good Die (KGD).<\/p>\n\n

        In addition to conventional wafer-level testing, testing individual dies after singulation provides an additional screening step before package assembly. Dies may experience different mechanical and thermal conditions during dicing and singulation, and die-level testing can help reduce the risk of defective dies being used in the final package.<\/p>\n\n

        SEMICS has developed a Single Die Prober for electrical testing of singulated dies. The system is designed to provide stable die handling and accurate probing under various die and test conditions. Key development areas include die handling stability, probing accuracy, support for different die sizes and warpage conditions, and thermal management for effective heat removal from the die during electrical testing.<\/p>\n\n

        This paper introduces the need for die-level testing and presents the system configuration and key development features of the SEMICS Single Die Prober.<\/p>\n<\/p>

        Sangyeong Han is a Mechanical Engineering Team Leader at SEMICS, working on the design and development of semiconductor probing systems. His work focuses on mechanical system design, precision motion and alignment, and probing mechanisms for wafer- and die-level testing. He has been involved in the development of various probing platforms, including wafer probers and die probers.<\/p><\/p><\/details>\n

        \n\t\ucd08\ub85d - \uc804\uae30 (Korean)<\/summary>\n

        AI \ubc0f HPC \uc2dc\uc7a5\uc758 \uc131\uc7a5\uacfc \ud568\uaed8 HBM, Chiplet \ub4f1 \uc5ec\ub7ec Die\ub97c \ud558\ub098\uc758 Package\uc5d0 \uc9d1\uc801\ud558\ub294 \uad6c\uc870\uac00 \uc99d\uac00\ud558\uace0 \uc788\ub2e4. Package\uc5d0 \uc0ac\uc6a9\ub418\ub294 Die \uc218\uac00 \uc99d\uac00\ud558\uba74\uc11c \uc870\ub9bd \uc804 \uac1c\ubcc4 Die\uc758 \ud488\uc9c8\uc744 \ud655\uc778\ud558\ub294 \uac83\uc774 \ub354\uc6b1 \uc911\uc694\ud574\uc9c0\uace0 \uc788\ub2e4. \ud2b9\ud788 \ud558\ub098\uc758 \ubd88\ub7c9 Die\ub85c \uc778\ud574 \ud568\uaed8 \uc870\ub9bd\ub41c \ub2e4\ub978 Good Die\uc640 Packaging Component\uae4c\uc9c0 \uc190\uc2e4\ub420 \uc218 \uc788\uae30 \ub54c\ubb38\uc5d0 KGD(Known Good Die) \ud655\ubcf4\uc758 \uc911\uc694\uc131\uc774 \ub192\uc544\uc9c0\uace0 \uc788\ub2e4.<\/p>\n\n

        \uae30\uc874 Wafer Level Test\uc640 \ub354\ubd88\uc5b4 Singulation \uc774\ud6c4 \uac1c\ubcc4 Die\ub97c Test\ud558\ub294 \uac83\uc740 Package Assembly \uc774\uc804\uc5d0 \ucd94\uac00\uc801\uc778 Screening\uc744 \uc218\ud589\ud560 \uc218 \uc788\ub294 \ubc29\ubc95\uc774\ub2e4. Dicing \ubc0f Singulation \uacfc\uc815\uc5d0\uc11c Die\ub294 Wafer \uc0c1\ud0dc\uc640 \ub2e4\ub978 \uae30\uacc4\uc801\u00b7\uc5f4\uc801 \uc870\uac74\uc5d0 \ub193\uc77c \uc218 \uc788\uc73c\uba70, Die-level Test\ub97c \ud1b5\ud574 \ubd88\ub7c9 Die\uac00 \ucd5c\uc885 Package\uc5d0 \uc0ac\uc6a9\ub418\ub294 Risk\ub97c \uc904\uc77c \uc218 \uc788\ub2e4.<\/p>\n\n

        SEMICS\ub294 Singulated Die\uc758 Electrical Test\ub97c \uc704\ud55c Single Die Prober\ub97c \uac1c\ubc1c\ud558\uc600\ub2e4. \ubcf8 \uc7a5\ube44\ub294 \ub2e4\uc591\ud55c Die \ubc0f Test \uc870\uac74\uc5d0\uc11c \uc548\uc815\uc801\uc778 Die Handling\uacfc \uc815\ubc00\ud55c Probing\uc774 \uac00\ub2a5\ud558\ub3c4\ub85d \uc124\uacc4\ud558\uc600\ub2e4. \uc8fc\uc694 \uac1c\ubc1c \ud56d\ubaa9\uc73c\ub85c\ub294 Die Handling \uc548\uc815\uc131, Probing Accuracy, \ub2e4\uc591\ud55c Die Size \ubc0f Warpage \ub300\uc751, \uadf8\ub9ac\uace0 Electrical Test \uc911 Die\uc5d0\uc11c \ubc1c\uc0dd\ud558\ub294 \uc5f4\uc744 \ud6a8\uacfc\uc801\uc73c\ub85c \uc81c\uac70\ud558\uae30 \uc704\ud55c Thermal Management\ub97c \uace0\ub824\ud558\uc600\ub2e4.<\/p>\n\n

        \ubcf8 \ubc1c\ud45c\uc5d0\uc11c\ub294 Die-level Test\uac00 \ud544\uc694\ud55c \ubc30\uacbd\uacfc \ud568\uaed8, SEMICS\uc5d0\uc11c \uac1c\ubc1c\ud55c Single Die Prober\uc758 System Configuration \ubc0f \uc8fc\uc694 \uac1c\ubc1c \ub0b4\uc6a9\uc744 \uc18c\uac1c\ud55c\ub2e4.<\/p>\n<\/p>

        \ud55c\uc0c1\uc601\uc740 SEMICS\uc5d0\uc11c Probing System\uc758 \uae30\uad6c \uc124\uacc4 \ubc0f \uac1c\ubc1c\uc744 \ub2f4\ub2f9\ud558\uace0 \uc788\ub294 \uae30\uad6c\uc124\uacc4\ud300\uc7a5\uc774\ub2e4. Wafer \ubc0f Die-level Test \uc7a5\ube44\uc758 \uae30\uad6c \uc2dc\uc2a4\ud15c \uc124\uacc4, \uc815\ubc00 \uad6c\ub3d9 \ubc0f Alignment, Probing Mechanism \uac1c\ubc1c\uc744 \uc8fc\uc694 \uc5c5\ubb34\ub85c \ud558\uace0 \uc788\uc73c\uba70, Wafer Prober\uc640 Die Prober\ub97c \ud3ec\ud568\ud55c \ub2e4\uc591\ud55c Probing Platform \uac1c\ubc1c\uc5d0 \ucc38\uc5ec\ud558\uace0 \uc788\ub2e4.<\/p><\/p><\/details>\n<\/div>\n<\/div>\n\t \n<\/div>

        <\/div><\/div><\/div>

        17:45<\/h1>\n<\/div><\/div><\/div><\/div>

        Lucky Draw<\/strong><\/h1>\n

        Door prizes for randomly selected attendees<\/span>
        \n(Must be present to win \/ void where prohibited)<\/p><\/span><\/div><\/div><\/div><\/div><\/div><\/div>

        18:00<\/h1>\n<\/div><\/div><\/div><\/div>

        TestConX EXPO Closes \/ Event Adjourns<\/strong><\/h1>\n<\/div><\/div><\/div><\/div><\/div><\/div>
        <\/div>
        <\/div><\/div><\/div>

        For any questions about the event or sponsorship contact us at [javascript protected email address]<\/span>