{"id":8579,"date":"2025-12-12T10:34:57","date_gmt":"2025-12-12T18:34:57","guid":{"rendered":"https:\/\/www.testconx.org\/premium\/?page_id=8579"},"modified":"2026-04-02T11:21:23","modified_gmt":"2026-04-02T18:21:23","slug":"testconx2026-tuesday","status":"publish","type":"page","link":"https:\/\/www.testconx.org\/premium\/testconx2026-tuesday\/","title":{"rendered":"TestConX 2026 – Tuesday"},"content":{"rendered":"
\"Image\"<\/span><\/div><\/div><\/div>

Rotate your smartphone to landscape or increase your browser width to see session descriptions.<\/h4><\/div><\/div><\/div><\/div>
Overview<\/span><\/div><\/div><\/a>
Sunday<\/span><\/div><\/div><\/a>
Monday<\/span><\/div><\/div><\/a>
Tuesday<\/span><\/div><\/div><\/a>
Wednesday<\/span><\/div><\/div><\/a><\/div><\/div>
EXPO<\/span><\/div><\/div><\/a><\/div><\/div><\/div><\/div>

Tuesday March 3, 2026<\/h1>\n<\/div><\/div><\/div><\/div><\/div>

7:00 a<\/h1>\n<\/div><\/div><\/div><\/div>

Continental Breakfast<\/h2>\n<\/div><\/div><\/div>

Start the day right and enjoy the continental breakfast while networking with other attendees.<\/p><\/div><\/div><\/div>

8:00 a<\/h1>\n<\/div><\/div><\/div><\/div>
\n
\n
Session 4<\/div>
Red Mountain Ballroom<\/div><\/div>
Market<\/div>
<\/div>

<\/p><\/div>

\n
\n“Turning Disruption into Advantage: A Socket Supplier\u2019s Perspective” \n<\/div>\n
\n
\n
\nJohn West\n <\/div>\n\t
\nYole Group\n\t <\/div>\n <\/div>\n
\n
\nNur Hilwani \"Nur\" Razi\n <\/div>\n\t
\nYole Group\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract (English)<\/summary>\n

The global semiconductor industry is undergoing profound structural change. The rapid expansion of fabless chipmakers - fuelled by evolving design ecosystems - and government actions such as subsidies, tariffs, and protectionist policies are redefining the balance of power across the supply chain. These shifts are not only altering where devices are designed, built, and tested, but also reshaping the dynamics of who buys, specifies, and influences the selection of test and burn-in sockets.\r\nThis presentation explores how these market disruptions are transforming the test socket landscape. It will highlight key trends driving this realignment, analyze their implications for socket suppliers, and offer strategic insights on how to adapt and thrive - turning industry turbulence into competitive advantage.<\/p>

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\n
\n“Evolving Dynamics in the Semiconductor Test Connectivity Market” \n<\/div>\n
\n
\n
\nGray Stephenson\n <\/div>\n\t
\nTechInsights\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract (English)<\/summary>\n

The semiconductor test connectivity market is undergoing significant transformation as device complexity, packaging diversity, and performance requirements continue to advance. This analysis explores market trends and forecasts across probe cards, test sockets, and device interface boards, highlighting how shifts in semiconductor design, application mix, and regional manufacturing are influencing demand. It examines growth patterns by device type and end use, evaluates technology transitions shaping connectivity requirements, and outlines the evolving role of test hardware within the broader semiconductor ecosystem over the next five years.<\/p>

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9:00 a<\/h1>\n<\/div><\/div><\/div><\/div>
\n
\n
Panel<\/div>
Red Mountain Foyer<\/div><\/div>
Panel<\/div>
<\/div>
\n
\n“Avoid Being Burned!” \n<\/div>\n\"\"<\/a>\"pdf-coming-soon\"<\/a>
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\nThe risk of damage to test interfaces such as sockets, probe cards, DUT\/load boards, etc. has increased significantly as the power requirement of devices continues to grow. With the explosion of mega devices - including some AI processors that regularly exceed 1000 W - the current and pin counts have grown exponentially exacerbating this issue. The challenging thermal environment also increases the potential for damage.\n<\/p>\n

\n This panel will explore how common this damage actually is along with best practices for design and operations to avoid damage.<\/p>\n\n

Join our panel of experts as they explore this \u201chot\u201d topic:<\/p><\/div>

<\/div><\/div><\/div>
\"Image\"<\/span><\/div>

Jerry Broz<\/strong> - Delphon & General Chair of SWTest Workshops<\/p><\/div><\/div><\/div><\/div>

\"Image\"<\/span><\/div>

Vijay Israni<\/strong> - ISE Labs<\/p><\/div><\/div><\/div><\/div>

\"Image\"<\/span><\/div>

Rich Karr<\/strong> - Texas Instruments (retired)<\/p><\/div><\/div><\/div><\/div>

\"Ken<\/span><\/div>

Ken Lanier<\/strong> - Teradyne<\/p><\/div><\/div><\/div><\/div>

\"Image\"<\/span><\/div>

Valts Treibergs<\/strong> - Johnstech International<\/p><\/div><\/div><\/div><\/div>

<\/div><\/div>

10:30 a<\/h1>\n<\/div><\/div><\/div><\/div>

Break & Networking<\/h2>\n<\/div><\/div><\/div>

Enjoy the break and networking time.<\/p><\/div>

<\/div><\/div>

11:00 a<\/h1>\n<\/div><\/div><\/div><\/div>
\n
\n
Session 5<\/div>
Red Mountain Ballroom<\/div><\/div>
PCB & Load Board<\/div>
<\/div>

<\/p><\/div>

\n
\n“Advancing Final Test Interface Hardware for AI & HPC Devices: Overcoming the Limits of Monolithic PCBs” \n<\/div>\n
\n
\n
\nEric Shoemaker\n <\/div>\n\t
\nDIS Tech\r\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract (English)<\/summary>\n

Final test -- especially for AI and high-performance computing (HPC) -- requires interface hardware capable of delivering extreme current, supporting high-speed signal delivery, and accommodating fine-pitch sockets. As device complexity increases, traditional monolithic PCB designs are reaching their physical and electrical limits, resulting in challenges with power delivery, signal integrity, and manufacturability.\r\n\r\nThis presentation introduces FusionLink, a modular interface architecture designed to meet the evolving demands of final test environments. FusionLink enables scalable, high-density PCB configurations with optimized stack-ups for power and signal delivery, while maintaining compatibility with standard materials and fabrication processes. The architecture supports high current (>6,000A), high-speed loopbacks (112\u2013224 Gbps), and fine-pitch routing down to 80\u00b5m -- making it ideal for socketed final test applications.\r\n\r\nReal-world implementations will be shared, demonstrating improvements in:\r\n - Signal integrity and return loss at high frequencies\r\n - Power delivery efficiency and thermal performance\r\n - Design flexibility for AI and HPC device test requirements\r\n - Reliability and cycle time compared to monolithic designs\r\n\r\nFusionLink offers a forward-looking solution for final test engineers facing the challenges of next-generation semiconductor devices and advanced packaging. By rethinking interface hardware architecture, it enables higher performance, better scalability, and faster time-to-volume in production test environments.\r\n<\/p>

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\n
\n“Reimagining the Device Under Test Interface, A Multi-Dimensional Problem” \n<\/div>\n
\n
\n
\nDon Edenfeld\n <\/div>\n\t
\nTeradyne\r\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract (English)<\/summary>\n

The insatiable demand for bandwidth drives competition for limited die shoreline area and system level power efficiency. Increasing interface performance leads to package level integration of electrical and optical interconnect that is orders of magnitude beyond what can be achieved with traditional packaging solutions. In the initial step, co-packaged copper and optical interconnect technologies provide relief. However, as the trend continues and the package becomes the system, connectorized topologies will dominate over traditional backside solutions. \r\n \r\nHistorically, the test interface has been dominated by 2D space transformation for power and I\/O interconnect to the device under test. As connectorized solutions emerge, and ultimately dominate in advanced designs, the test interface becomes a 3D problem. \r\n \r\nLeft to its own devices, this will result in substantial engineering investment in product specific solutions for multiple axis mechanical interconnect actuation. The device interface problem has historically been solved by the 2D \u201cloadboard\u201d. Now is the opportunity, how must we evolve to enable the next generation of 3D interconnect?\r\n<\/p>

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\n
\n“Surface Finish Options for Spring Probe Applications” \n<\/div>\n
\n
\n
\nColin Poedtke\n <\/div>\n\t
\nUyemura USA\n\t <\/div>\n <\/div>\n<\/div>\n\"\"<\/a>\"pdf-coming-soon\"<\/a>
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12:30 p<\/h1>\n<\/div><\/div><\/div><\/div>

Lunch<\/h2>\n<\/div><\/div><\/div>

Lunch is served. Enjoy the break and networking time.<\/p><\/div><\/div><\/div>

1:30 p<\/h1>\n<\/div><\/div><\/div><\/div>
\n
\n
Session 6<\/div>
Red Mountain Ballroom<\/div><\/div>
Test Methods<\/div>
<\/div>

<\/p><\/div>

\n
\n“A Full-Scenario Shmoo Solution for Enhancing ChipTest Efficiency” \n<\/div>\n
\n
\n
\nSteve Xie\n <\/div>\n\t
\nAdvantest (China) Management Co., Ltd.\r\n\t <\/div>\n <\/div>\n
\n
\nChelsea Zhou\n <\/div>\n\t
\nAdvantest (China) Management Co., Ltd.\r\n\t <\/div>\n <\/div>\n
\n
\nLang Liu\n <\/div>\n\t
\nAMLogic\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract (English)<\/summary>\n

The Shmoo tool is a commonly used tool in the chip testing process. With Shmoo, engineers can conveniently probe various characteristics of chips, such as chip corner information and minimum operating voltage. However, as chip testing requirements become more complex, in actual Shmoo testing, we may need to meet additional demands, such as scanning the maximum operating frequency, Vmin\/Vmax values, the minimum\/maximum voltage for parallel testing of chip pins or adjusting the Shmoo step based on register contents instead of voltage and current parameters. Unfortunately, the original Shmoo solutions of ordinary testing platforms cannot satisfy the above requirements.\r\n\r\nBased on this, we have developed a highly practical Shmoo solution under the operating environment of V93000. This solution needs to address the following issues and limitations in the Smartest8 environment:\r\n\r\n1.\tHow to call the original test item instances to execute any test item in test method.\r\n2.\tHow to implement pass\/fail judgment for non-functional test items.\r\n3.\tHow to meet the requirements for different types of Shmoo scanning parameters.\r\n4.\tHow to handle Vmin\/Vmax value analysis with Shmoo holes.\r\n5.\tHow to standardize the STDF data log output\r\n\r\nTo solve the above problems, this solution can directly call the functions of any test item instance through the new API interface executor, thus enabling highly customized requirements for various Shmoo tests, such as the combined testing requirements of multiple test items, test item group Shmoo testing requirements, or the packaged testing requirements of test items with complex execution logic. Meanwhile, through flexible program architecture design, it can meet the requirements of different Shmoo scanning units, such as register content scanning and vector content scanning. It also integrates an extensible backend data processing framework, which can set various unit pass\/fail judgment conditions, such as frequency and voltage\/current. In response to the actual common requirements for Shmoo data processing, the solution also provides a Vmin\/Vmax extraction function that can intelligently skip\/identify Shmoo holes. Shmoo holes are eliminated through a special algorithm, thereby greatly improving the accuracy and coverage of Vmin\/Vmax data. And finally, we have defined a standard STDF shmoo data output format for best data result analysis efficiency.\r\n\r\nWith the help of this tool, in actual projects, the coverage of Shmoo scanning has been expanded from the original 30% to over 90%, the data correlation time after Shmoo scanning has been shortened by 50%, and more effective data results have been provided. Moreover, with the highly customized execution framework, the offline construction efficiency of Shmoo test items has been improved by 90%. In addition, its flexible structural design can adapt to more complex testing requirements in the future.\r\n<\/p>

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\n
\n“Enhancing Operational Efficiency and Reducing Costs in Known Good Die Handling with Universal Micro-Textured Carrier Tray” \n<\/div>\n
\n
\n
\nJerry Broz\n <\/div>\n\t
\nGel-Pak\r\n\t <\/div>\n <\/div>\n
\n
\nVictoria Tran\n <\/div>\n\t
\nGel-Pak\r\n\t <\/div>\n <\/div>\n
\n
\nRaj Varma\n <\/div>\n\t
\nGel-Pak\r\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract (English)<\/summary>\n

The rapid evolution of semiconductor packaging and integration has exposed the limitations of traditional, custom-molded trays for handling Known Good Die (KGD). This work highlights the development and advantages of universal, pocketless carriers utilizing engineered micro-textured films, which eliminate the need for custom trays, streamline inventory, and enable flexible, reliable handling of diverse die sizes throughout advanced manufacturing and test processes.\r\n<\/p>

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\n
\n“AutoML-Driven Pipeline for Real-time Semiconductor Test Optimization via Cloud-IoT Integration” \n<\/div>\n
\n
\n
\nVincent \"Fangmin\" Chu\n <\/div>\n\t
\nAdvantest\r\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract (English)<\/summary>\n

As semiconductor devices grow in complexity and chiplet-based architectures become mainstream, traditional static test plans are increasingly inadequate. To improve test efficiency and accuracy, dynamic, data-driven strategies\u2014such as adaptive test limits, predictive analytics, and real-time decision-making\u2014are becoming essential. Machine learning (ML) enables data feedforward and feedback across test stages (e.g., parametric test, wafer sort, final test, system-level test), supporting optimizations like Vmin prediction, shift-left testing, and multivariate outlier screening.\r\n\r\nHowever, implementing data-driven test optimization faces three major challenges, especially within the fabless\u2013OSAT (Outsourced Semiconductor Assembly and Test) manufacturing model:\r\n1.\tFabless companies often lack dedicated data science teams, making ML adoption difficult for test engineers.\r\n2.\tReal-time inference requires low latency\u2014ideally within a single device touchdown.\r\n3.\tModel deployment, monitoring, retraining, and selective data ingestion must be orchestrated across a dynamic, geographically distributed test infrastructure, bridging upstream operations with OSAT test floors.\r\n\r\nTo address these challenges, we developed a scalable architecture powered by an AutoML (Automated Machine Learning) pipeline integrated with cloud and IoT (Internet of Things) technologies. AutoML automates key steps in the ML lifecycle\u2014such as data preprocessing, model selection, and hyperparameter tuning\u2014enabling test engineers to apply ML without deep expertise. In our implementation, AutoGluon handles these tasks, while deployment, monitoring, and retraining are orchestrated through integrated cloud-IoT infrastructure. Cloud services provide scalable compute and storage, allowing fabless teams to manage models independently of OSAT environments. For low-latency inference, edge servers near testers run ML workloads locally, ingesting die-level features from the cloud when feedforwarded data from prior test stages is required. IoT technologies serve as the synchronization layer, enabling secure, real-time bi-directional data and control exchange between cloud and edge.\r\n\r\nThe architecture was implemented using Advantest ACS Gemini, an AWS-hosted digital twin environment for ML-driven test development. Key components include:\r\n\u2022 AWS S3 \u2013 used to aggregate test datalogs and trigger ETL (extract, transform, load) jobs for model training, enabling scalable and centralized data management.\r\n\u2022 AutoGluon \u2013 an open-source AutoML toolkit by AWS that automates data preprocessing, model selection, and hyperparameter tuning, allowing test engineers to build models without deep ML expertise.\r\n\u2022 AWS IoT \u2013 enables automated provisioning of IoT infrastructure in the production environment including deploying lightweight IoT clients on edge servers and tester host controllers, and real-time bi-directional communication between cloud and edge, supporting data exchange, control signaling, and synchronization across distributed test environments.\r\n\u2022 Cloud-IoT orchestration \u2013 coordinates the full ML lifecycle, including cloud-to-edge deployment of containerized models, transmission of selected test-derived die features for inference, and edge-to-cloud alerts for retraining upon drift detection.\r\n\r\nSecurity is addressed through AWS IoT\u2019s identity and policy management, ensuring secure interactions from initial provisioning to ongoing data exchange.\r\n\r\nThis presentation outlines the architecture, implementation, and use cases\u2014highlighting Vmin prediction\u2014and shares insights from deploying this solution, demonstrating how the AutoML-driven pipeline, with cloud-IoT integration, delivers real-time, data-driven optimization in semiconductor test with intelligence, automation, and scalability.\r\n<\/p>

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\n
\n“CRAFT: Contextual Retrieval & Assembly Framework for Test Programs” \n<\/div>\n
\n
\n
\nNavnath Raut\n <\/div>\n\t
\nAdvantest\r\n\t <\/div>\n <\/div>\n
\n
\nMykola Zakharchuk\n <\/div>\n\t
\nAdvantest\r\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract (English)<\/summary>\n

This presentation introduces the Contextual Retrieval and Assembly Framework for Test Programs (CRAFT), a safety-first framework for applying large language model (LLM) agents in Automated Test Equipment (ATE) program development. Instead of relying on unconstrained code generation, CRAFT leverages structured retrieval, explicit dependency tracking, and safe assembly primitives to automate repetitive editing and propagation tasks while keeping engineers in control. By reframing the role of LLMs from \u201ccode guessers\u201d to \u201ccontextual assemblers,\u201d CRAFT delivers safer, faster, and more reliable test program development.\r\n<\/p>

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3:30 p<\/h1>\n<\/div><\/div><\/div><\/div>

TestConX EXPO<\/h2>\n<\/div><\/div><\/div>

Continue to explore the great exhibits at the TestConX EXPO. There is always something new to see or someone new to meet. Refreshments and drinks are served but don't spoil your appetite before the TestConX Social...<\/p><\/div><\/div><\/div>

6:30 p<\/h1>\n<\/div><\/div><\/div><\/div>

TestConX Social Event<\/h2>\n<\/div><\/div><\/div>

Continue the networking with your colleagues and industry friends at the TestConX Social Event.<\/p>\n

There will be lots of fun and great food in store!<\/p><\/div><\/div><\/div>

9:00 p<\/h1>\n<\/div><\/div><\/div><\/div>

Adjourn<\/h2>\n<\/div><\/div><\/div><\/div><\/div>

Program subject to change without notice.<\/em><\/p><\/div><\/div><\/div><\/div>

Overview<\/span><\/div><\/div><\/a>
Sunday<\/span><\/div><\/div><\/a>
Monday<\/span><\/div><\/div><\/a>
Tuesday<\/span><\/div><\/div><\/a>
Wednesday<\/span><\/div><\/div><\/a><\/div><\/div>
EXPO<\/span><\/div><\/div><\/a><\/div><\/div><\/div><\/div><\/div>\n","protected":false},"excerpt":{"rendered":"

Rotate your smartphone to landscape or increase your browser width to see session descriptions.OverviewSundayMondayTuesdayWednesdayEXPOTuesday March 3, 2026 7:00 a Continental Breakfast Start the day right and enjoy the continental breakfast while networking with other attendees.8:00 a Session 4Red Mountain BallroomMarket “Turning Disruption into Advantage: A Socket Supplier\u2019s Perspective” John West Yole Group Nur Hilwani “Nur” Razi Yole Group Abstract (English) … <\/p>\n

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