{"id":8578,"date":"2025-12-03T15:15:38","date_gmt":"2025-12-03T23:15:38","guid":{"rendered":"https:\/\/www.testconx.org\/premium\/?page_id=8578"},"modified":"2026-04-06T21:41:45","modified_gmt":"2026-04-07T04:41:45","slug":"testconx2026-monday","status":"publish","type":"page","link":"https:\/\/www.testconx.org\/premium\/testconx2026-monday\/","title":{"rendered":"TestConX 2026 – Monday"},"content":{"rendered":"
\"Image\"<\/span><\/div><\/div><\/div>

Rotate your smartphone to landscape or increase your browser width to see session descriptions.<\/h4><\/div><\/div><\/div><\/div>
Overview<\/span><\/div><\/div><\/a>
Sunday<\/span><\/div><\/div><\/a>
Monday<\/span><\/div><\/div><\/a>
Tuesday<\/span><\/div><\/div><\/a>
Wednesday<\/span><\/div><\/div><\/a><\/div><\/div>
EXPO<\/span><\/div><\/div><\/a><\/div><\/div><\/div><\/div>

Monday March 2, 2026<\/h1>\n<\/div><\/div><\/div><\/div><\/div>

7:30 a<\/h1>\n<\/div><\/div><\/div><\/div>

Continental Breakfast<\/h2>\n<\/div><\/div><\/div>

Start the day right and enjoy the continental breakfast while networking with other attendees.<\/p><\/div><\/div><\/div>

8:30 a<\/h1>\n<\/div><\/div><\/div><\/div>
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Welcome<\/div>
Red Mountain Ballroom<\/div><\/div>
Opening Remarks<\/div>
Welcoming remarks from the General Chair, Ira Feldman<\/div>

<\/p><\/div><\/div>\n\t \n<\/div><\/div>

9:00 a<\/h1>\n<\/div><\/div><\/div><\/div>
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Keynote<\/div>
Red Mountain Ballroom<\/div><\/div>
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\n“Burn-In at the Inflection Point \u2014 Supporting HPC, Chiplets, and CPO in Production Test” \n<\/div>\n\"\"<\/a>\"pdf-coming-soon\"<\/a>
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\"Vijay<\/span>

Vijay Israni<\/strong>
ISE Labs<\/p><\/div><\/div>

Burn-in is at a critical inflection point, driven by the rapid rise of high-performance computing (HPC), high-power AI accelerators, chiplet-based architectures, and co-packaged optics (CPO). These technologies are fundamentally reshaping power density, thermal behavior, and failure mechanisms, placing new demands on both engineering methodology and production infrastructure.<\/span><\/p>\n<\/div><\/div><\/div><\/div>

This keynote examines the direction of burn-in as it expands across the manufacturing flow from wafer-level burn-in and Known Good Die (KGD) screening to package- and system-level production burn-in. High-power chiplets and CPO devices introduce localized hot spots, asymmetric loading, and steep thermal gradients that challenge traditional chamber-based approaches. In response, multi-zone thermal control, targeted cooling, and tighter coordination between electrical stress and thermal management are becoming essential to achieve meaningful and repeatable reliability screening.<\/span><\/p>\n

The discussion further addresses how wafer-level and early package-level burn-in are being leveraged to improve yield learning, reduce downstream risk, and support scalable KGD strategies for heterogeneous integration. As cost, throughput, and time-to-market pressures intensify, production burn-in must remain tightly correlated to system-level reliability while operating within the constraints of high-volume manufacturing.<\/span><\/p>\n

Taken together, these shifts redefine the role of burn-in from a downstream qualification activity to an integrated, production-critical capability that enables reliable deployment of next-generation HPC, chiplet, and CPO platforms. The direction outlined reflects both current production realities and the emerging requirements that will shape test and reliability strategies over the coming decade<\/span>.<\/b><\/p>\n<\/div>