{"id":6912,"date":"2023-12-22T19:22:36","date_gmt":"2023-12-23T03:22:36","guid":{"rendered":"https:\/\/www.testconx.org\/premium\/?page_id=6912"},"modified":"2025-03-28T13:28:41","modified_gmt":"2025-03-28T20:28:41","slug":"testconx2024-tuesday","status":"publish","type":"page","link":"https:\/\/www.testconx.org\/premium\/testconx2024-tuesday\/","title":{"rendered":"TestConX 2024 – Tuesday"},"content":{"rendered":"
\"Image\"<\/span><\/div><\/div><\/div>

Rotate your smartphone to landscape or increase your browser width to see session descriptions.<\/h4><\/div><\/div><\/div><\/div>
Overview<\/span><\/div><\/div><\/a>
Sunday<\/span><\/div><\/div><\/a>
Monday<\/span><\/div><\/div><\/a>
Tuesday<\/span><\/div><\/div><\/a>
Wednesday<\/span><\/div><\/div><\/a><\/div><\/div>
EXPO<\/span><\/div><\/div><\/a><\/div><\/div><\/div><\/div>

Tuesday March 5, 2024<\/h1>\n<\/div><\/div><\/div><\/div><\/div>

7:00 a<\/h1>\n<\/div><\/div><\/div><\/div>

Continental Breakfast<\/h2>\n<\/div><\/div><\/div>

Start the day right and enjoy the continental breakfast while networking with other attendees.<\/p><\/div><\/div><\/div>

8:00 a<\/h1>\n<\/div><\/div><\/div><\/div>
\n
\n
Session 4<\/div>
Red Mountain Ballroom<\/div><\/div>
Market<\/div>
<\/div>

<\/p><\/div>

\n
\n“Evolving Semiconductor Testing Trends” \n<\/div>\n
\n
\n
\nPanchami Phadke\n <\/div>\n\t
\nTechInsights\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract - Biography (English)<\/summary>\n

Embark on a journey through the intricate realm of Semiconductor testing with this comprehensive\r\npresentation. Discover the latest trends dictating the trajectory of the Probe Cards and Socket markets,\r\ndelving into the pivotal roles these components play in the semiconductor landscape. Our exploration\r\nextends beyond market trends, scrutinizing the influential factors driving the dynamic evolution of Test\r\nrequirements. A special focus will be on the detailed interplay of quantity and types of packaging,\r\nshedding light on the nuanced demands of contemporary testing scenarios. From emerging technologies\r\nto shifting market dynamics, this presentation offers a nuanced understanding of the multifaceted\r\nfactors shaping semiconductor testing strategies. Stay informed and empowered as we navigate through\r\nthe intricacies of the current state and anticipate the future directions in Semiconductor testing.<\/p><\/p>

Panchami is a Market Research Analyst at TechInsights. Her primary focus is Test Connectivity Systems\r\nreports such as Probe Card, Sockets and Device Interface Boards. Her work also focuses on the market\r\nanalysis of semiconductor tests both in Memory and Non-memory markets.<\/p>\r\n

Panchami graduated from California State University, Los Angeles with a Master of Science majoring in\r\nMathematics. She also has an MBA in Finance from RIT University, Bangalore, India. She has published a\r\nMaster Thesis about using Markov Chain and Python to analyze and predict the Stock Market trend.\r\nPanchami has also published many academic papers in Indian Research Journal, SAGE Student Research\r\nConference, etc. and presented at TestConX China 2022, TestConX 2023 at Mesa, Arizona, SW Test 2023\r\nat Carlsbad, CA, TestConX Korea and China 2023 and SW Test Taiwan 2023 as well.<\/p><\/p><\/details>\n\"\"<\/a>

<\/div>\"PDF-Icon<\/a> Presentation Download<\/a><\/div>\n
\n
\n“Trends in Advanced Packaging and the Impact on Test” \n<\/div>\n
\n
\n
\nJohn West\n <\/div>\n\t
\nYole\n\t <\/div>\n <\/div>\n<\/div>\n\"\"<\/a>
<\/div>\"PDF-Icon<\/a> Presentation Download<\/a><\/div>\n<\/div>\n\t \n\n
\n
Session 4<\/div>
Red Mountain Ballroom<\/div><\/div>
Thermal<\/div>
<\/div>

<\/p><\/div>

\n
\n“Testing Innovative Thermal Interface Materials for Semiconductor Test” \n<\/div>\n
\n
\n
\nDave Saums\n <\/div>\n\t
\nDS&A LLC\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract (English)<\/summary>\n

Introduction and Outline\r\n\r\nThis discussion seeks to describe testing practices for innovative thermal interface materials that are designed specifically for semiconductor test applications, or which are directly applicable. Thermal interface materials (TIMs) are available from hundreds of vendors (not all of whom are developers and manufacturers) more than fourteen highly varied major types, designed for a very wide variety of types of applications.\r\n\r\nCurrent industry standard test methodologies are outlined in ASTM D 5470-17, developed by over three decades by a working committee of industry thermal engineers. This methodology provides a guideline for how test systems may be designed and constructed and for the general principals involved in testing TIMs. However, the very large number of different material types requires an understanding of the principal material categories, the intended purposes for the major types, and the differences encountered in thermal performance testing and reliability testing.\r\n\r\nThis presentation will therefore include:\r\n\r\n\u2022\tAn overview of the fourteen principal material categories and definitions for intended applications;\r\n\u2022\tIdentification of specific material types that are relevant to semiconductor test systems and applications;\r\n\u2022\tAn overview of the basic testing methodologies; \r\n\u2022\tA description on a step-by-step basis of recommended testing practices and how standardized test stands are designed to generate the most consistent, accurate, and repeatable measurements;\r\n\u2022\tExamples of test data output for a variety of different TIM types, including specifically TIM products designed to address challenging semiconductor test requirements that are not commonly found in other electronics applications;\r\n\u2022\tExamples of test challenges for developing new metallic TIM concepts;\r\n\u2022\tExamples of unusual reliability testing for contact-and-release cycles for semiconductor test TIMs.\r\n\r\nThe purpose is to add to the tool kit and improve understanding for these thermal materials that are critical to successful semiconductor test and semiconductor operation and reliability. \r\n\r\n\r\nDave Saums, Principal, DS&A LLC:\r\n\r\nDave has forty-five years\u2019 experience in many aspects of electronics thermal management, for manufacturers and developers of military\/aerospace high-reliability precision fans, high-volume heat sinks and liquid cold plates, advanced thermal interface materials, CTE-matched rigid thermal materials and substrates, and two-phase pumped dielectric liquid cooling systems. Dave operates a full-time consulting business addressing these products and markets, working with vendors, test equipment manufacturers, and system OEMs. \r\n\r\nDave has previously conducted a tutorial for TestConX on thermal interface material classifications and has also given presentations at TestConX and BiTS.<\/p>

<\/p><\/details>\n\"\"<\/a>

<\/div>\"PDF-Icon<\/a> Presentation Download<\/a><\/div>\n
\n
\n“Surface roughness effect on thermal performance of graphene enhanced thermal interface materials” \n<\/div>\n
\n
\n
\nAmos Nkansah\n <\/div>\n\t
\nSHT Smart High Tech AB\n\t <\/div>\n <\/div>\n
\n
\nOscar Nordin\n <\/div>\n\t
\nChalmers University of Technology\n\t <\/div>\n <\/div>\n
\n
\nKristoffer Harr\n <\/div>\n\t
\nSHT Smart High Tech AB\n\t <\/div>\n <\/div>\n
\n
\nJin Chen\n <\/div>\n\t
\nSHT Smart High Tech AB\n\t <\/div>\n <\/div>\n
\n
\nJohan Liu\n <\/div>\n\t
\nChalmers University of Technology\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract (English)<\/summary>\n

Power densities in integrated circuits are ever increasing. Consequently, efficient heat dissipation from chip die and heat sink is becoming a serious hindrance to further improving integrated electronics.Recently, graphene-enhanced thermal interface materials (GT-TIM) have showed remarkable thermal conductivity and conformity. In this talk we present how surface roughness on the GT-TIM impacts conformity and thermal impedance for pressures below 100 kPa, and how the influence of surface roughness is of less import at higher pressures.<\/p>

<\/p><\/details>\n\"\"<\/a>

<\/div>\"PDF-Icon<\/a> Presentation Download<\/a><\/div>\n<\/div>\n\t \n<\/div><\/div>

10:00 a<\/h1>\n<\/div><\/div><\/div><\/div>
\n
\n
Poster<\/div>
Red Mountain Ballroom<\/div><\/div>
Poster<\/div>
<\/div>

<\/p><\/div>

\n
\n“New Heat Resistant Dicing Tape for Final Test Solution\r\n” \n<\/div>\n
\n
\n
\nReona \"Leo\" Yokota\n <\/div>\n\t
\nMitsui Chemicals Tohcello, Inc.\n\t <\/div>\n <\/div>\n
\n
\nEiji Hayashishita\n <\/div>\n\t
\nMitsui Chemicals Tohcello, Inc.\n\t <\/div>\n <\/div>\n
\n
\nAkimitsu Morimoto\n <\/div>\n\t
\nMitsui Chemicals Tohcello, Inc.\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract (English)<\/summary>\n

We\u2019ve developed a novel dicing tape with good heat resistant property. This tape is good for small devices for automotive applications to do tri-temperature test with film flame handler.<\/p>

<\/p><\/details>\n<\/div>\n

\n
\n“High Speed Socket for Package Chip Test up to 40 GHz Using Polyimide-based Grounded Coplanar Waveguide Transmission.” \n<\/div>\n
\n
\n
\nTae Kyun \"Steve\" Kim\n <\/div>\n\t
\nPMT (PROTEC MEMS TECHNOLOGY)\n\t <\/div>\n <\/div>\n
\n
\nYong Ho \"YH\" Cho\n <\/div>\n\t
\nPMT (PROTEC MEMS TECHNOLOGY)\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract (English)<\/summary>\n

With the ongoing reduction in the size and increasing density of semiconductor devices, there is a growing demand for contact solutions that facilitate high-speed testing in automotive, 5G, and artificial intelligence-based devices. The need for new solutions that can accommodate fine-pitch, high-speed, and high-density requirements remains. This study proposes a novel radio frequency high-speed socket for package chip testing, supporting frequencies of up to 40 GHz. It employs polyimide-based grounded coplanar waveguide transmission lines.\r\n\r\nA hybrid grounded coplanar waveguide is utilized, where the width of the transmission lines and the ground design's shape vary to meet the current-carrying capacity required for high radio frequency power channels. Following a hybrid design concept, we fabricate a hybrid grounded coplanar waveguide circuit using polyimide-based multilayers via a one-time built-up process, utilizing three-dimensional Micro-Electro-Mechanical Systems (3D MEMS) techniques. This fabrication ensures a robust structure extending up to the contact tip, thereby ensuring reliable signal transmission and integrity.\r\n\r\nFurthermore, the design incorporates various factors crucial to signal integrity, including impedance matching, scattering parameters, and jitters. The performance of the proposed probe card is validated through comprehensive simulations and measurements, demonstrating the feasibility and effectiveness of the design through suitable experiments. The obtained results confirm the exceptional performance of the proposed high-speed socket in package chip testing scenarios and its suitability for a wide range of package chip testing applications, supporting frequencies up to 40 GHz. Its ability to ensure reliable signal transmission, combined with consideration of key signal integrity parameters, makes it a valuable tool in the electronic packaging industry.<\/p>

<\/p><\/details>\n<\/div>\n

\n
\n“High Speed Burn in Test Socket with Stamped Spring Probe Pins” \n<\/div>\n
\n
\n
\nHyung Jun \"AJ\" Park\n <\/div>\n\t
\nIWIN\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract (English)<\/summary>\n

Test pins for semiconductor process are one of the most challenging interconnect applications in electronics due to the combination of harsh operating conditions and high performance requirements.\r\nBurn in test did not require high performance pins previously, but customers look for burn in pins good for high frequency test and providing longer traveling distance at low cost. \r\nThe research and development efforts presented, the poster, \r\n-\tdescribe new technologies for high performance spring probe pins good for burn in test, good for high speed test, high pin count sockets at high frequency with low cost. \r\n-\tinclude with spring probe pins, in excellent and ideal design, made by stamping process and fully automated assembly process, improved electrical\/mechanical performance for various kinds of packages. \r\n-\talso include pins by stamping, how to deal with big volume order with short lead time, how to match with automated socket assembly process, and how to maintain stable quality control. \r\nThe research data presented support the theory that a spring probe provides low\/stable contact resistance, high electrical performance, and how to maintain reliable signal thru longer life of pins. \r\nThe poster will give details of research and development to evolve to the current state of knowledge and describe current product offering and their related performance characteristics.<\/p>

<\/p><\/details>\n<\/div>\n

\n
\n“Spring Probe Pins for Extremely High Frequency\/High Pin Count” \n<\/div>\n
\n
\n
\nSang Yang \"Samuel\" Pak\n <\/div>\n\t
\nIWIN C., Ltd.\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract (English)<\/summary>\n

Test pins for semiconductor process are one of the most challenging interconnect applications in electronics due to the combination of harsh operating conditions and high performance requirements.\r\nOrdinary understanding is the length of the pin should be very short to realize a good performance at high frequency test, such as 80 GHz or higher. \r\nHowever, there are the cases the test socket accommodating many pins such as 8,000 pin count, a very short pin cannot be used in spite of the high performance.\r\nWith these back grounds, there shall be a pin with new technology, providing long traveling distance, but also good for high frequency test. \r\n-\tThe research and development efforts presented, describe new technologies for spring probe pins good for high frequency test and providing long traveling distance. \r\n-\tThe poster will include how to design the coax socket with the pin with new technology.\r\n-\tThe poster will also include, how to deal with big volume order with short lead time, how to match with automated socket assembly process, and how to maintain stable quality control. \r\nThe poster will give details of research and development to evolve to the current state of knowledge and describe current product offering and their related performance characteristics.<\/p>

<\/p><\/details>\n<\/div>\n

\n
\n“Execution Challenges with Qualification of Chip on Flex Technology” \n<\/div>\n
\n
\n
\nRakeshkumar Jain\n <\/div>\n\t
\nTexas Instruments Inc.\n\t <\/div>\n <\/div>\n
\n
\nRamana Tadepalli\n <\/div>\n\t
\nTexas Instruments Inc.\n\t <\/div>\n <\/div>\n<\/div>\n<\/div>\n
\n
\n“Test equipment for High Frequency test environment\r\n” \n<\/div>\n
\n
\n
\nJungRyeol \"Kevin\" Choi\n <\/div>\n\t
\nSensorview Co., Ltd.\n\t <\/div>\n <\/div>\n
\n
\nSumin Park\n <\/div>\n\t
\nSensorview Co., Ltd.\n\t <\/div>\n <\/div>\n<\/div>\n<\/div>\n
\n
\n“RF Performance Test in Different Pitch & Thickness of Matrix Contact Sheets\r\n” \n<\/div>\n
\n
\n
\nBeck Srikoulabouth\n <\/div>\n\t
\nShin-Etsu Polymer America\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract (English)<\/summary>\n[see 'abstracts' folder - in TestConX 2024 folder]

<\/p><\/details>\n<\/div>\n<\/div>\n\t \n<\/div><\/div>

11:00 a<\/h1>\n<\/div><\/div><\/div><\/div>
\n
\n
Session 5<\/div>
Red Mountain Ballroom<\/div><\/div>
Operations \/ Machine Learning<\/div>
<\/div>

<\/p><\/div>

\n
\n“Spring Probe with Tip Scrubbing” \n<\/div>\n
\n
\n
\nJiachun \"Frank\" Zhou\n <\/div>\n\t
\nSmiths Interconnect\n\t <\/div>\n <\/div>\n
\n
\nJason \"Jason \" Qi\n <\/div>\n\t
\nSmiths Interconnect\n\t <\/div>\n <\/div>\n
\n
\nFrank Liu\n <\/div>\n\t
\nSmiths Interconnect\n\t <\/div>\n <\/div>\n
\n
\nQiaoyun \"Gloria\" Bao\n <\/div>\n\t
\nSmiths Interconnect\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract (English)<\/summary>\n

The semiconductor test industry has traditionally used spring pin technology for BGA, LGA, QFN, and QFP devices, while the cantilever scrubbing contact design has been used in peripheral segments to remove surface oxides and contaminants. However, the vertical spring probe technology used in the array segment allows for a dense population of individual contacts in the array with more Z-axis compliance.\r\n While both contact technologies require maintenance and performance monitoring to ensure optimal results during testing cycles, the piercing effect of spring probes on gold pads has been a challenge due to the buildup of surface oxides. Additionally, the cantilever type has been associated with expensive PCB damage.\r\n\r\nTo address these issues, Smiths Interconnect develop a new technology that combines the scrub motion of a cantilever contact with the modular benefits of a spring probe. The design includes horizontal movement during the downward stroke of the device to break surface oxides, provide stable and reliable contact, and inflict no damage to the PCB. This solution offers a single solution to achieve optimal testing results without the drawbacks associated with traditional contact technologies.\r\nThis paper will introduce socket with this spring probe and its impacts on performance. Extensive test results and contact surfaces with and without scrubbing on pads, including lab tests and QFN chip testing, will be shared with audience in this paper. The advantages of using this type spring probes in testing QFN package, such as no offset PCB pads, better signal integrity with coaxial structure, etc, will be discussed. More importantly, this new technology will provide another contact option for IC chip testing industry.<\/p>

<\/p><\/details>\n\"\"<\/a>

<\/div>\"PDF-Icon<\/a> Presentation Download<\/a><\/div>\n
\n
\n“Test time and Cost Reduction Using Intelligent Prediction from ML Models” \n<\/div>\n
\n
\n
\nLisa Taubensee\n <\/div>\n\t
\nAdvantest\n\t <\/div>\n <\/div>\n
\n
\nYiwen Liao\n <\/div>\n\t
\nAdvantest\n\t <\/div>\n <\/div>\n
\n
\nMatthias Sauer\n <\/div>\n\t
\nAdvantest\n\t <\/div>\n <\/div>\n
\n
\nSarah Rottacker\n <\/div>\n\t
\nAdvantest\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract (English)<\/summary>\n

There is a large benefit in saved time, material and test costs to being able to catch bad devices earlier in the entire wafer process. There is also often large volumes of data available from various stages. (Eg: wafer test, package test, final test, system level test) In this paper we show how a machine learning (ML) algorithm was used to build and validate a model which predicts final test pass\/fail based on wafer sort data for an Advantest chip. In this case the model was trained on existing data and finally packaged as a python package which allows making the decision\/prediction efficient in a production or post production environment. This saves packaging and testing costs for parts which pass wafer sort testing, however are expected to fail final test. It was determined a cost savings of 40% at final test could be achieved. Considerations for monitoring have also been taken into account. This brings a new level of intelligence to testing from Advantest as this algorithm and approach is not limited to prediction of final test results however opens up a range of forward predictive machine learning applications.<\/p>

<\/p><\/details>\n\"\"<\/a>

<\/div>\"PDF-Icon<\/a> Presentation Download<\/a><\/div>\n
\n
\n“Test Socket-Pin Tracker: Advanced Socket-Pin Qualification and Performance Monitoring with Big Data Analytics” \n<\/div>\n
\n
\n
\nEugene Khoo\n <\/div>\n\t
\nExperior Technology\n\t <\/div>\n <\/div>\n
\n
\nCharlotte Wai\n <\/div>\n\t
\nExperior Technology\n\t <\/div>\n <\/div>\n
\n
\nJiawei \"Joce\" Lin\n <\/div>\n\t
\nExperior Technology\n\t <\/div>\n <\/div>\n
\n
\nSeow-Woon Ho\n <\/div>\n\t
\nExperior Technology\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract (English)<\/summary>\n

In the ever-evolving landscape of socket-pin design, development and production, the need for empirically driven optimization for efficiency has become greater. To address this growing need, we are introducing the principles of what we call \u2018enhanced qualification\u2019. It begins with a collective effort between test development, product engineering and manufacturing teams to cover the functional and repeatability requirements from NPI to high volume manufacturing. \r\n These requirements can now be empirically tracked throughout the lifespan of a product with ExSA-, a software solution that has pin-level traceability and data analytics capabilities. This solution enables us to move beyond the traditional realm of making decisions with simulation driven data, or data collected over a small sample size, which can vary widely in reality. With ExSA-, a complete, accurate and real-world characterization of any socket-pin solution can be built. Utilizing this proven baseline, we can now introduce a different paradigm - cost per insertion. \r\n This approach disrupts the existing models of machine vision system used for automated inspection and rigid maintenance practices\/schedules by enabling real-time, condition-based data monitoring and predictive maintenance. Now every socket-pin solution can be characterized by product\/device and ATE type to drive surgical engineering and management decisions. \r\n With the ExSA- solution, we can take on the connector challenges of today and anticipate those of tomorrow with precision and foresight.\r\n\r\nAbstract\r\nIn the ever-evolving landscape of socket-pin design, development and production, the need for empirically driven optimization for efficiency has become greater to ensure product quality and performance. Test sockets, the critical interface between test equipment and semiconductor devices, play a pivotal role as the critical factor in the whole test setup. How do we comprehensively characterize a socket-pin solution in the environment it will be used in throughout its lifespan from development to qualification to deployment in high volume manufacturing? How can we ensure that a tester-handler set-up which is qualified with high performance sockets achieves the maximum number of insertions before maintenance or replacements are needed? We have an answer with the tracking of these key factors - socket usage duration, pin insertion count and machine downtime due to sockets and\/or pins. \r\n\r\nThis presentation introduces our ExSA- Test Socket-Pin Tracker, an application developed with big data analytics techniques, capable of providing an overview of an entire factory\u2019s socket-pin performance by insertion count against yield trends for all devices and the equipment\/components they are tested on\/with. This enables ExSA- users to make optimised, data-driven decisions for their day-to-day test operations. With ExSA-, we move away from making decisions with simulated data and gravitate instead towards live data from the field. With complete, accurate and real-world characterization of any socket-pin solution, we can now introduce a different paradigm - cost per insertion. \r\n \r\n\r\nIn this presentation, we delve into the key features and capabilities of our ExSA- Test Socket-Pin Tracker, highlighting its ability to provide a holistic view of any test socket performance. By continuously monitoring and analyzing insertion counts, we have built a database with unprecedented insights into the performance, health, and lifecycle of sockets and pins across different platforms and different devices. This database has enabled us to move into the predictive maintenance phase where pins are swapped out based on historical performance with a high level of accuracy. Maintenance practices can now include real-time data to enable comprehensive knowledge to qualify set ups, analyze socket wear, failure patterns, evaluate socket performance, correlate yields to insertion counts, to improve socket and pin reliability and inventory management. \r\n\r\nThis presentation also provides real-world case studies and step-by-step analysis with practical applications to highlight the tangible benefits and competitive advantages that ExSA- Test Socket Insertion Tracker offers. Cost per insertion data can be used as a baseline to predict several vectors of performance like throughput, efficiency, life cycle cost and reliability. These enables a more accurate approach to resource and investment allocation by removing unknowns or replacing estimates with real-world data. This can be powerful and disruptive at the same time as it can be used to hold all players in the semiconductor ecosystem to a higher standard of transparency and accountability when it comes to the performance and reliability or a socket-pin solution. \r\n\r\nWith ExSA-\u2019s big data analytic techniques, real-time monitoring, and seamless integration with our predictive maintenance system, we can take on the connector challenges of today and anticipate those of tomorrow with precision and foresight.<\/p>

<\/p><\/details>\n\"\"<\/a>

<\/div>\"PDF-Icon<\/a> Presentation Download<\/a><\/div>\n<\/div>\n\t \n<\/div><\/div>

12:30 pm<\/h1>\n<\/div><\/div><\/div><\/div>

Lunch<\/h2>\n<\/div><\/div><\/div>

Lunch is served. Enjoy the break and networking time.<\/p><\/div><\/div><\/div>

1:30 pm<\/h1>\n<\/div><\/div><\/div><\/div>
\n
\n
Session 6<\/div>
Red Mountain Ballroom<\/div><\/div>
Batteries & Electric Vehicles<\/div>
<\/div>

<\/p><\/div>

\n
\n“Impact of PWM resolution in a digital feedback loop precision power supplies” \n<\/div>\n
\n
\n
\nTaras Dudar\n <\/div>\n\t
\nTexas Instruments\n\t <\/div>\n <\/div>\n
\n
\nShaury Anand\n <\/div>\n\t
\nTexas Instruments\n\t <\/div>\n <\/div>\n
\n
\nRamana Tadepalli\n <\/div>\n\t
\nTexas Instruments\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract (English)<\/summary>\n

Precision DC source is used in variety of test applications. Battery formation and testing requires a precise high power bidirectional DC\/DC power supplies. Analog feedback loop has been traditionally used to achieve current and voltage precision. The designers have moved away from analog to digital control due to design flexibility and circuit optimization. However, digital control requires precise PWM to regulate the output current and voltage to less than \u00b1 0.02% of F.S accuracy. The paper discusses impact of PWM resolution on the output ripple of DC\/DC power supply, and techniques to reduce the ripple.<\/p>

<\/p><\/details>\n\"\"<\/a>

<\/div>\"PDF-Icon<\/a> Presentation Download<\/a><\/div>\n
\n
\n“The Trends and Future Solutions in Battery Test” \n<\/div>\n
\n
\n
\nHao Liu\n <\/div>\n\t
\nTexas Instruments\n\t <\/div>\n <\/div>\n
\n
\nRamana Tadepalli\n <\/div>\n\t
\nTexas Instruments\n\t <\/div>\n <\/div>\n
\n
\nTaras Dudar\n <\/div>\n\t
\nTexas Instruments\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract (English)<\/summary>\n

In the age of renewable energy, the demand for batteries is on the rise. Battery manufacturing now demands greater precision, enhanced efficiency, cost-effective solutions. In this presentation, several trends in battery testing are discussed and potential technical solutions are proposed. \r\nAnalog control is crucial in scenarios where fast transient time is critical, whereas digital control loops offer advantages in battery charging systems, leveraging microprocessor computing power, and having the capability to tweak for multiple systems. High precision, fast sampling rate ADC, and the right microprocessor are vital components.\r\nSerial charging, as opposed to charging battery cells individually, can reduce cable costs with higher input voltage, which requires higher standoff voltage for the components. There is also a trade-off of having a bypass circuit for each cell or a group of cells. \r\nWith the emergence of SiC and GaN technology, higher switching frequency to control the power management component in the system is needed to achieve better efficiency with higher channel density. To generate such a high frequency PWM control signal, analog technology may be considered. \r\nImpedance spectroscopy is gaining prominence over DCIR (direct current internal resistance) and ACIR (alternating current internal resistance) for its ability to capture more data points across various frequencies. This enables the early detection of thermal runaway in batteries. For implementation, the device should be able to generate AC signals at various frequencies and measure real and imaginary impedance.\r\nTo expedite the analysis of self-discharge, measuring leakage current while maintaining the same voltage level is more efficient than relying solely on OCV (open-circuit voltage). This necessitates high-precision small current generation and measurement.\r\nIn our presentation we intend to review the state of battery test and discuss possibilities of battery tester integration that present improvements to the state of the art.<\/p>

<\/p><\/details>\n\"\"<\/a>

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\n
\n“Production-Test of Battery Cells and Packs & EV-Connectors using Spring-Probes and Contacts” \n<\/div>\n
\n
\n
\nMatthias \"Matt\" Zapatka\n <\/div>\n\t
\nINGUN USA, Inc.\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract (English)<\/summary>\n

In this paper, we present an overview of state-of-the art and emerging spring-contact technologies to make temporary contact with individual battery cells and modules\/packs as well as EV connectors (for example on inverters or other circuitry) for the purpose of production test. Spring-contacts are used for a variety of applications, ranging from conventional PCBA-test with \u201cbed of nails\u201d test fixtures to fine-pitch probes for test socket applications. The use of such components for cell testing may sound like a trivial task but it\u2019s actually a very complex process. Minute details such as the correct tip style choice, spring-force selection or plating materials decide whether a cell can be successfully tested or not. In our paper we are covering the following topics (a) a general introduction how a spring-loaded test probe \/ contact looks like (b) introduction to applications for the battery industry, which include formation, weld-joint test, OCV and ACIR test (c) ways to optimize tip-to-target-performance for critical parameters such as the contact resistance (d) techniques for temperature control (sensing) and how to cool test probes, especially for high-density applications. (e) preventive maintenance aspects such as probe tip cleaning. We conclude the paper with a brief outlook what may be next on the horizon when it comes to battery test (for example for testing solid state batteries) and include a \u201cwish list\u201d \/ open invitation for the engineering audience to submit feedback to drive further research for the battery and EV connector test niche.<\/p>

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\n“Qualification Execution Challenges with High Voltage Devices” \n<\/div>\n
\n
\n
\nJustin Wadley\n <\/div>\n\t
\nTexas Instruments\n\t <\/div>\n <\/div>\n<\/div>\n
\n\tAbstract (English)<\/summary>\n[see 'abstracts' folder - in TestConX 2024 folder]

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<\/div>\"PDF-Icon<\/a> Presentation Download<\/a><\/div>\n<\/div>\n\t \n<\/div><\/div>

3:30 p<\/h1>\n<\/div><\/div><\/div><\/div>

TestConX EXPO<\/h2>\n<\/div><\/div><\/div>

Continue to explore the great exhibits at the TestConX EXPO. There is always something new to see or someone new to meet. Refreshments and drinks are served but don't spoil your appetite before the TestConX Social...<\/p><\/div><\/div><\/div>

6:30 p<\/h1>\n<\/div><\/div><\/div><\/div>

TestConX Social Event<\/h2>\n<\/div><\/div><\/div>

Continue the networking with your colleagues and industry friends at the TestConX Social Event.<\/p>\n

There will be lots of fun and great food in store!<\/p><\/div><\/div><\/div>

9:00 p<\/h1>\n<\/div><\/div><\/div><\/div>

Adjourn<\/h2>\n<\/div><\/div><\/div><\/div><\/div>

Program subject to change without notice.<\/em><\/p><\/div><\/div><\/div><\/div>

Overview<\/span><\/div><\/div><\/a>
Sunday<\/span><\/div><\/div><\/a>
Monday<\/span><\/div><\/div><\/a>
Tuesday<\/span><\/div><\/div><\/a>
Wednesday<\/span><\/div><\/div><\/a><\/div><\/div>
EXPO<\/span><\/div><\/div><\/a><\/div><\/div><\/div><\/div><\/div>\n","protected":false},"excerpt":{"rendered":"

Rotate your smartphone to landscape or increase your browser width to see session descriptions.OverviewSundayMondayTuesdayWednesdayEXPOTuesday March 5, 2024 7:00 a Continental Breakfast Start the day right and enjoy the continental breakfast while networking with other attendees.8:00 a Session 4Red Mountain BallroomMarket “Evolving Semiconductor Testing Trends” Panchami Phadke TechInsights Abstract – Biography (English) Embark on a journey through the intricate realm of … <\/p>\n

Read More<\/a><\/div>\n","protected":false},"author":548,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-6912","page","type-page","status-publish","hentry","no-post-thumbnail"],"_links":{"self":[{"href":"https:\/\/www.testconx.org\/premium\/wp-json\/wp\/v2\/pages\/6912","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.testconx.org\/premium\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.testconx.org\/premium\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.testconx.org\/premium\/wp-json\/wp\/v2\/users\/548"}],"replies":[{"embeddable":true,"href":"https:\/\/www.testconx.org\/premium\/wp-json\/wp\/v2\/comments?post=6912"}],"version-history":[{"count":14,"href":"https:\/\/www.testconx.org\/premium\/wp-json\/wp\/v2\/pages\/6912\/revisions"}],"predecessor-version":[{"id":7071,"href":"https:\/\/www.testconx.org\/premium\/wp-json\/wp\/v2\/pages\/6912\/revisions\/7071"}],"wp:attachment":[{"href":"https:\/\/www.testconx.org\/premium\/wp-json\/wp\/v2\/media?parent=6912"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}