TestConX has been postponed to May 10-13 due to Coronavirus
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Tuesday May 12, 2020
Start the day right and enjoy the continental breakfast while networking with other attendees.
It is essential that interface hardware is properly validated before deploying in high volume manufacturing (HVM). As test complexity and requirements have increased, so has the need to properly complete the validation using handling equipment ideally in a lab environment. A new methodology introduced allows many environment variables to be tested simultaneously including temperature and current during cycle testing. The method presented leads to shorter lead-times, quicker ramps, less downtime, and reduced time to market.
Radio frequency complementary metal oxide semiconductors (RFCMOS) system-on-chip (SoC) devices primarily used in automotive radar for advanced driver-assistance systems (ADAS) applications require specialized test cells. The integration of test cells with the right automated test equipment (ATE), innovative contact technology, and tri-temperature capable part handlers to support 81 GHz socketed test solutions will be described.
Lastly, a wafer probe test cell utilizing built-in self-test (BiST) for second generation 80 GHz radar transceiver modules with high level integration of transmit, receive, and voltage-controlled oscillator (TX, RX, & VCO) functions in one device will be presented.
This session provides a deeper understanding of test hardware, especially sockets, electrical signal integrity (SI) requirements of crosstalk, impedance, eye height, etc. The printed circuit board (PCB) itself has the potential to become a major crosstalk contributor in the socket-to-IC interface area. A SI analysis of the socket combined with the PCB interface will demonstrate the need for comprehensive analysis if meaningful results are desired. Next the signal integrity issues of co-axial spring-pin sockets for high-speed device test will be compared to solutions using rubber sockets with impedance matching. As high-speed data rates increase rapidly for bus protocols like PCIE4.0, higher levels of electrical isolation are required in all aspects of the test hardware especially the socket. The last presentation compares the isolation and signal quality provided by different socket types including coaxial and non-matched configurations.
Lunch is served. Enjoy the break and networking time.
Advances in semiconductor manufacturing creates significant challenges in validating silicon designs and performance. A creative solution using modular multi-domain power delivery platform for sub-7 nm system-on-chip (SOC) silicon validation is presented. And there are new tester requirements for harsh radiation environment testing for soft error rate measurement. The process of qualifying and releasing a new package level tester for proton high energy beam testing is described. Next, at the system-level there many challenges in bench testing and validation of silicon due to complexity in system board integration. A breakthrough solution to this problem will be presented that simulates the physical oscilloscope function with a field programmable gate array (FPGA) to improve the overall test time. Finally, while 3D packaging provides high performance it introduces thermal and mechanical challenges due to the package complexity. A novel split-socket concept is shown that bypasses the memory and provides a conductive path directly to the 3D package.
Continue to explore the great exhibits at the TestConX EXPO. There is always something new to see or someone new to meet. Refreshments and drinks are served but don't spoil your appetite before the TestConX Social...
TestConX Social Event
Continue the networking with your colleagues and industry friends at the TestConX Social Event.
Program subject to change without notice.