TestConX 2020

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TestConX has been postponed to May 10-13 due to Coronavirus

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Tuesday May 12, 2020

7:00 a

Continental Breakfast

Start the day right and enjoy the continental breakfast while networking with other attendees.

8:00 a

Session 4
Red Mountain Ballroom
Total Solutions
Test Cell Integration & Automated Test Equipment

It is essential that interface hardware is properly validated before deploying in high volume manufacturing (HVM). As test complexity and requirements have increased, so has the need to properly complete the validation using handling equipment ideally in a lab environment. A new methodology introduced allows many environment variables to be tested simultaneously including temperature and current during cycle testing. The method presented leads to shorter lead-times, quicker ramps, less downtime, and reduced time to market.

Radio frequency complementary metal oxide semiconductors (RFCMOS) system-on-chip (SoC) devices primarily used in automotive radar for advanced driver-assistance systems (ADAS) applications require specialized test cells. The integration of test cells with the right automated test equipment (ATE), innovative contact technology, and tri-temperature capable part handlers to support 81 GHz socketed test solutions will be described.

Lastly, a wafer probe test cell utilizing built-in self-test (BiST) for second generation 80 GHz radar transceiver modules with high level integration of transmit, receive, and voltage-controlled oscillator (TX, RX, & VCO) functions in one device will be presented.

“Building the Next Generation Test Method Standard: Matching the Production Enviroment with In-House Testing”
Jason Mroczkowski
Cohu
“Pin Savers: Enabling ATE testing 81GHz mmWave RFCOM SoC Device”
Guor-Chaur Jung
Texas Instruments
James "Mr. T" Tong
Texas Instruments
“Quad-Site Production Wafer Probing of 77-81 GHz Automotive Radar Devices”
Marty Cavegn
Cohu
Jason Mroczkowski
Cohu
Jory J. Twitchell
NXP Semiconductors
“Lifecycle discussion follow-up”
James "Mr. T" Tong
Texas Instruments
Jason Mroczkowski
Cohu

10:00 a

Poster Session
Red Mountain Foyer
Poster Session
Break & Networking
“Implementing a DUT to Tester Interface for mmWave Devices”
Dale Johnson
Marvin Test Solutions
David Hu
Marvin Test Solutions
“High Frequency Electrical Characterization of New 3D MEMS Coaxial Socket for High Performance Package”
Taekyun "Steve" Kim
Microfriend
Yongho Cho
Microfriend
Jongmyeon Lee
Microfriend
Shinkwon Han
Microfriend
“Spring Probe Pins for One Piece Housing Design”
Sang Yang "Samuel" Pak
IWIN
“Spring Probe Pins for Extremely High Speed Test up to/beyond -1db@80Ghz”
Hyungjun "AJ" Park
IWIN
“Developing a Wafer Connector with 200,000 Interconnection Pads”
Larre Nelson
Paricon
“RF Multiple Cavity Structure of PCBs Using Coaxial Metal Walls”
Takasuke Hashimoto
JC Electronics Corporation
“Elastomer Interposer Structure for BGA Testing”
Tony Smith
Phoenix Test Arrays
Frank Bumb
Phoenix Test Arrays
“An Effective CCC Evaluation Method of Probes Using a NiCr Wafer”
Dongil You
Samsung Electronics Co.
Gyu-Yeol Kim
Samsung Electronics Co.
Changhyun Cho
Samsung Electronics Co.
Sang-Kyu Yoo
Samsung Electronics Co.
“Development of 5G Electrical Contact for use in Test, Burn-In, & Tri-Temp ”
Mike Ramsey
Plastronics
Larry Furman
Plastronics
“Ultra-fine Pitch Socket Qualification”
John Ronk
J2M Test Solutions Inc.
Michael Ricci
Rika Denshi America, Inc.

11:00 a

Session 5
Red Mountain Ballroom
True Waveforms
Electrical Signal Integrity

This session provides a deeper understanding of test hardware, especially sockets, electrical signal integrity (SI) requirements of crosstalk, impedance, eye height, etc. The printed circuit board (PCB) itself has the potential to become a major crosstalk contributor in the socket-to-IC interface area. A SI analysis of the socket combined with the PCB interface will demonstrate the need for comprehensive analysis if meaningful results are desired. Next the signal integrity issues of co-axial spring-pin sockets for high-speed device test will be compared to solutions using rubber sockets with impedance matching. As high-speed data rates increase rapidly for bus protocols like PCIE4.0, higher levels of electrical isolation are required in all aspects of the test hardware especially the socket. The last presentation compares the isolation and signal quality provided by different socket types including coaxial and non-matched configurations.

“Crosstalk - the other PAM4 Constraint”
Gert Hohenwarter
GateWave Northern, Inc.
“Signal Analysis & Comparison of Coaxial Test Interfaces”
Chris Mack
TSE
BoHyun "BH" Kim
TSE
Yunchan "YC" Nam
TSE
“Study of Test Hardware Isolation Performance for PCIE4.0”
Yoinjun "YJ" Shi
TwinSolution Technology (Shanghai)

12:30 p

Lunch

Lunch is served. Enjoy the break and networking time.

1:30 p

Session 6
Red Mountain Ballroom
Creative Checking
Validation

Advances in semiconductor manufacturing creates significant challenges in validating silicon designs and performance. A creative solution using modular multi-domain power delivery platform for sub-7 nm system-on-chip (SOC) silicon validation is presented. And there are new tester requirements for harsh radiation environment testing for soft error rate measurement. The process of qualifying and releasing a new package level tester for proton high energy beam testing is described. Next, at the system-level there many challenges in bench testing and validation of silicon due to complexity in system board integration. A breakthrough solution to this problem will be presented that simulates the physical oscilloscope function with a field programmable gate array (FPGA) to improve the overall test time. Finally, while 3D packaging provides high performance it introduces thermal and mechanical challenges due to the package complexity. A novel split-socket concept is shown that bypasses the memory and provides a conductive path directly to the 3D package.

“Design of Modular Ultra-Low Voltage Power Delivery System for Sub-7nm SOC Validation”
Xiao-Ming Gao
Intel
“New Tester Qualification using Parallel Test & Correlation for Soft Error Rate Measurements”
Krishna Mohan Chavali
Globalfoundries US Inc
Joshua Dragula
Globalfoundries US Inc
“99% Validation Efficiency Through Cloud Power Sequencing”
See Tien "Angie" Ng
Intel
Seong Guan "SG" Ooi
Intel
“Thermal Challenges in Enabling Validation & Test of 3D Package on Package”
Ying-feng Pang
Intel
Arunima Panigrahy
Intel
Jack Mumbo
Intel
Michael Apodaca
Intel
Victor Polyanko
Intel

3:30 p

TestConX EXPO

Continue to explore the great exhibits at the TestConX EXPO. There is always something new to see or someone new to meet. Refreshments and drinks are served but don't spoil your appetite before the TestConX Social...

6:30 p

TestConX Social Event

Continue the networking with your colleagues and industry friends at the TestConX Social Event.

9:30 p

Adjourn

Program subject to change without notice.