Among the challenges that post-silicon validation faces are silicon configuration capability and a growing product portfolio. By design, Intel develops generalized silicon products to support a wide-range of possible use cases. Physical system configurations are driven by memory (types, speeds, size) and thousands of possible input-output (IO) options to meet the needs of original equipment manufacturers (OEMs) and original device manufacturers (ODMs). New and emerging markets such as Autonomous Driving, Artificial Intelligence, 5G, and Cloud are growing the product portfolio. Together, silicon configuration and new markets, the number of silicon products to validate has more than doubled in the last five years.

Not only are post-silicon validation hardware solution providers challenged with supporting more products, the hardware solutions have become more complex. Among these more diverse number of products are larger packages/higher ball count/tighter pitch (driven by higher levels of integration) and/or products with higher power density as a result of higher performance. Compounding the challenges of validators and hardware providers is the need to provide faster time to market (TTM) at lower development costs across a growing product portfolio.

An overview of how hardware strategies and platforms have evolved and adapted to meet these challenges of post-silicon validation will be presented. It will include three specific case studies: scaling power measurement and challenges of >340 A; scaling socketing solutions and challenges with >300 µm of warpage; and scaling thermal tools and challenges for >500 W products with -40 C temperature requirement.

John Kelbert is a Principal Engineer within Intel’s Infrastructure & Platform Solutions Group. He joined in 1993 as a system validation hardware engineer, quickly progressing up to validation platform System Architect. Throughout his career at Intel, John played an active role in the evolution of Intel's validation hardware strategy and solutions and is presently driving the development of key technologies for future validation solutions.

Amy Xia is a mechanical and thermal architect at Intel. She is responsible for leading the development of solutions and qualification of next generation technologies in the areas of Socket, Retention, and Thermal to enable Validation and Manufacturing of across all major market segments. After receiving her PhD degree in fluid dynamics, she has been with Intel for more than 12 years.

Tong Wa (Tony) Chao is a mechanical engineer at Intel since 2004. His main research and development interests have been focused on mechanical design and stress analysis for system validation hardware and electronics packaging.