
Sunday March 3, 2019
There will be breaks including refreshments to provide networking time for Tutorial attendees.
Please note: attendance at the tutorial will be limited. Please sign-up early to not miss out!
Noon to 6:00 pm
6:30 p
Welcome Reception
7:30 p
Dinner
8:30 p
E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided market research and technology trend analysis in semiconductor packaging since 1987. She is the co-author of How to Make IC Packages (by Nikkan Kogyo Shinbunsha), a columnist with Printed Circuit Design & Fab/Circuits Assembly, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She is a senior member of IEEE EPS and is an IEEE EPS Distinguished Lecturer. She is a member of SEMI, SMTA, IMAPS, and MEPTEC. She received the IMAPS GBC Partnership award in 2012 and the Daniel C. Hughes, Jr. Memorial Award in 2018. She is an IMAPS Fellow. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.
The high cost of moving to the next semiconductor technology node is changing the role of packaging and assembly in the electronics industry. New packaging solutions are being adopted to achieve the economic advantages that were previously met with silicon scaling. These options include silicon interposers, fan-out wafer level packages, and system-in-package. Some high-performance options are considered homogeneous integration, where die are partitioned. Others are classified as heterogeneous integration, including solutions in which some die functions are fabricated on the latest nodes, combined with other die fabricated on older less expensive nodes and linked together in the package. Combinations of memory and logic in the same package are increasingly common. Challenges for packaging and assembly in this new era include chip package interaction (CPI) for devices fabricated with low-k and ultra-low-k (ULK) dielectrics. Substrate warpage remains an issue and the need for known good die is becoming increasingly important. Test considerations factor into package choices. This presentation discusses the packaging changes and some of the issues being faced.